kopia lustrzana https://github.com/mycr0ft/upython_si5351
Removed start() and stop() commands and added phase_delay option
rodzic
d6c4f6e6a4
commit
593c8c598c
17
SI5351.py
17
SI5351.py
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@ -105,18 +105,14 @@ class SI5351:
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return
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def write8( self, register, value):
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self.i2c.start()
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buffera = bytearray(1)
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buffera[0] = value & 0xff
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self.i2c.writeto_mem( self.address, register, buffera)
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self.i2c.stop()
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return
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def read8( self, register, value):
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self.i2c.start()
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buffera = bytearray(1)
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self.i2c.readfrom_mem_into( self.address, register, buffera)
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self.i2c.stop()
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return
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@ -239,7 +235,7 @@ class SI5351:
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return None
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def setupMultisynth( self, output, div, num, denom, pllsource):
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def setupMultisynth( self, output, div, num, denom, pllsource, phase_delay):
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assert self.initialized == True, "device not initialized"
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assert output in [0,1,2], "output out of range"
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assert div > 3, "div out of range"
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@ -266,7 +262,7 @@ class SI5351:
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#
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# P3[19:0] = c
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if num==0:
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if num==0 and phase_delay == 0.0:
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# integer mode
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P1 = 128 *div -512
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P2 = num
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@ -289,6 +285,15 @@ class SI5351:
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self.write8( baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) )
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self.write8( baseaddr+6, (P2 & 0x0000FF00) >> 8)
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self.write8( baseaddr+7, (P2 & 0x000000FF))
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if phase_delay != 0.0:
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assert phase_delay > 0 and phase_delay <= 1.0, "Invalid phase delay, must be in [0,1]"
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ph_delay_reg = SI5351_REGISTER_165_CLK0_INITIAL_PHASE_OFFSET + output
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delay = int(phase_delay * (div + num/denom))
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assert delay < 128, "Phase delay too large for selected PLL divisor"
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self.write8(ph_delay_reg, delay)
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self.write8(SI5351_REGISTER_177_PLL_RESET, (1 << 7) | (1 << 5))
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# Configure the clk control and enable the output
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clkControlReg = 0x0F # 8mA drive strength, MS0 as CLK0 source, Clock not inverted, powered up
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