SPI.md tidy up table.

pull/1/head
Peter Hinch 2019-12-17 17:40:57 +00:00
rodzic 912e6629d5
commit 801504bfb9
1 zmienionych plików z 10 dodań i 10 usunięć

Wyświetl plik

@ -21,16 +21,16 @@ Any SPI interface may be used. The table below assumes a Pyboard running SPI(2)
as per the test program. To wire up a single EEPROM chip, connect to a Pyboard
as below. Pin numbers assume a PDIP package (8 pin plastic dual-in-line).
| EEPROM | PB | Signal |
|:-------:|:---:|:------:|
| 1 CS | Y5 | SS/ |
| 2 SO | Y7 | MISO |
| 3 WP/ | 3V3 | 3V3 |
| 4 Vss | Gnd | Gnd |
| 5 SI | Y8 | MOSI |
| 6 SCK | Y6 | SCK |
| 7 HOLD/ | 3V3 | 3V3 |
| 8 Vcc | 3V3 | 3V3 |
| EEPROM | Signal | PB | Signal |
|:-------:|:------:|:---:|:------:|
| 1 | CS | Y5 | SS/ |
| 2 | SO | Y7 | MISO |
| 3 | WP/ | 3V3 | 3V3 |
| 4 | Vss | Gnd | Gnd |
| 5 | SI | Y8 | MOSI |
| 6 | SCK | Y6 | SCK |
| 7 | HOLD/ | 3V3 | 3V3 |
| 8 | Vcc | 3V3 | 3V3 |
For multiple chips a separate CS pin must be assigned to each chip: each one
must be wired to a single chip's CS line. Multiple chips should have 3V3, Gnd,