Added sync section

STM32F405-Timer-Triggering.md

@@ -25,3 +25,31 @@ The update_event is also generated by:
 * update generation through the slave mode controller
 
 refer to Timer app note: DM00042534.pdf
+
+##Timer synchronisation
+
+A Master can control a slave Timer using a Trigger TRGO.
+A Timer is slaved if its ITRx is connected to a Slave and the Master is set to use TRGO
+
+Trigger outputs from the Master can be selected from:
+* Reset:
+  * UG bit from EGR reg is used as TRGO
+* Enable:
+  * Counter enable is used as TRGO. 
+  * Used to start several timers at the same time or control window for Slave start
+* Update:
+  * the update_event is TRGO.
+  * e.g. a master timer can act as a prescaler for a slave timer.
+* Compare pulse:
+  * as soon as a capure or match occurs TRGO goes high when CC1IF flag is to be set
+* OC1REF: use OC1REF as TRGO
+* OC2REF: use OC2REF as TRGO
+* OC3REF: use OC3REF as TRGO
+* OC4REF: use OC4REF as TRGO
+
+###Master mode:
+1. Configure the Timer
+2. Select Trigger output to be used
+  * in CR2 reg - set MSM bits
+3. Enable Master/slave mode
+  * in SMCR reg - enable MSM bit