Fix markdown

STM32F405-Timer-Triggering.md

@@ -11,7 +11,7 @@ For example, you can see below that TIM8 can be triggerd by TIM1.
 * Counter mode is set using the TIMx_CR1 reg and CMS bits as indicated in the example below.
 * The counter mode sets whether the update_event occurs on overflow and/or underflow of the Timer.
 
-###Example for internal trigger
+### Example for internal trigger
 Internal trigger clock mode 1 (ITRx)
 TIM_CLK is replaced by ITRx_CLK which is the internal trigger freq mapped to timer Trigger input TRGI.
 
@@ -47,7 +47,7 @@ Trigger outputs from the Master can be selected from:
 * OC3REF: use OC3REF as TRGO
 * OC4REF: use OC4REF as TRGO
 
-###Master mode:
+### Master mode:
 1. Configure the Timer
 2. Select Trigger output to be used
   * in CR2 reg - set MSM bits