kopia lustrzana https://github.com/micropython/micropython
220 wiersze
8.5 KiB
Python
220 wiersze
8.5 KiB
Python
#!/usr/bin/env python3
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#
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# This file is part of the MicroPython project, http://micropython.org/
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#
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# The MIT License (MIT)
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#
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# Copyright (c) 2021 Philipp Ebensberger
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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"""Evaluate FlexRAM configuration and generate startup code."""
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import re
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import argparse
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# Regex for linker script configuration
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ocram_regex = r"^\s*ocrm_size\s*=\s*(?P<size>.*);"
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dtcm_regex = r"^\s*dtcm_size\s*=\s*(?P<size>.*);"
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itcm_regex = r"^\s*itcm_size\s*=\s*(?P<size>.*);"
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# Regex for GPR register base define in NXL hal
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gpr_base_regex = r"^.*IOMUXC_GPR_BASE\s*\((?P<base_addr>\w*)u\)"
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# Regex for FlexRAM parameters in NXP HAL
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fsl_ram_bank_size_regex = r"^.*FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE\s*\((?P<size>\w*)\)"
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fsl_bank_nbr_regex = (
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r"^.*FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS\s*\((?P<number>\w*)\)"
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)
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"""
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According to AN12077:
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The minimum configuration of OCRAM is 64 KB. This is required
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due to ROM code requires at least 64 KB of RAM for its execution.
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2.1.1.1. Static configuration - Page 4
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"""
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ocram_min_size = 0x00010000 # 64 KB
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# Value parser
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def mimxrt_default_parser(defines_file, features_file, ld_script):
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with open(ld_script, "r") as input_file:
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input_str = input_file.read()
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#
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ocram_match = re.search(ocram_regex, input_str, re.MULTILINE)
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dtcm_match = re.search(dtcm_regex, input_str, re.MULTILINE)
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itcm_match = re.search(itcm_regex, input_str, re.MULTILINE)
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with open(defines_file, "r") as input_file:
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input_str = input_file.read()
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mcu_define_file_match = re.search(gpr_base_regex, input_str, re.MULTILINE)
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with open(features_file, "r") as input_file:
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input_str = input_file.read()
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fsl_ram_bank_size_match = re.search(fsl_ram_bank_size_regex, input_str, re.MULTILINE)
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fsl_bank_nbr_match = re.search(fsl_bank_nbr_regex, input_str, re.MULTILINE)
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#
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extract = {
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"ocram_size": int(ocram_match.group("size"), 16),
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"dtcm_size": int(dtcm_match.group("size"), 16),
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"itcm_size": int(itcm_match.group("size"), 16),
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"gpr_base_addr": int(mcu_define_file_match.group("base_addr"), 16),
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"fsl_ram_bank_size": int(fsl_ram_bank_size_match.group("size")),
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"fsl_bank_nbr": int(fsl_bank_nbr_match.group("number")),
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}
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# Evaluate configuration
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if extract["ocram_size"] < ocram_min_size:
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raise ValueError("OCRAM size must be at least {:08X}!".format(ocram_min_size))
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if (extract["ocram_size"] % extract["fsl_ram_bank_size"]) != 0:
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raise ValueError("Configuration invalid!")
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# Check if DTCM and ITCM size is either multiple of 32k or 4k,8k or 16k
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if extract["dtcm_size"] != 0x0:
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if extract["dtcm_size"] % extract["fsl_ram_bank_size"] != 0:
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if extract["dtcm_size"] not in (0x00000000, 0x00001000, 0x00002000, 0x00004000):
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raise ValueError("Configuration invalid!")
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if extract["itcm_size"] != 0x0:
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if extract["itcm_size"] % extract["fsl_ram_bank_size"] != 0:
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if extract["itcm_size"] not in (0x00000000, 0x00001000, 0x00002000, 0x00004000):
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raise ValueError("Configuration invalid!")
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#
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return extract
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# Code generators
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def mimxrt_default_gen_code(extract_dict):
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flexram_bank_cfg = "0b"
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avail_flexram = extract_dict["fsl_ram_bank_size"] * extract_dict["fsl_bank_nbr"]
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if (
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extract_dict["ocram_size"] + extract_dict["dtcm_size"] + extract_dict["itcm_size"]
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) > avail_flexram:
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raise ValueError("Configuration exceeds available FlexRAM!")
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bit_patterns = (
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(extract_dict["ocram_size"], "01"),
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(extract_dict["dtcm_size"], "10"),
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(extract_dict["itcm_size"], "11"),
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)
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for size, pattern in bit_patterns:
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for _ in range(0, size, extract_dict["fsl_ram_bank_size"]):
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flexram_bank_cfg += pattern
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# Generate GPR Register config
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print(".equ __iomux_gpr14_adr, 0x{:08X}".format(extract_dict["gpr_base_addr"] + 0x38))
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print(".equ __iomux_gpr16_adr, 0x{:08X}".format(extract_dict["gpr_base_addr"] + 0x40))
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print(".equ __iomux_gpr17_adr, 0x{:08X}".format(extract_dict["gpr_base_addr"] + 0x44))
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print(
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".equ __iomux_gpr17_value, 0x{:08X} /* {}k OCRAM, {}k DTCM, {}k ITCM */".format(
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int(flexram_bank_cfg, 2),
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extract_dict["ocram_size"] // 1024,
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extract_dict["dtcm_size"] // 1024,
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extract_dict["itcm_size"] // 1024,
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)
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)
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def mimxrt_106x_gen_code(extract_dict):
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flexram_bank_cfg = "0b"
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avail_flexram = extract_dict["fsl_ram_bank_size"] * extract_dict["fsl_bank_nbr"]
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flexram_configurable_ocram = (
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extract_dict["ocram_size"] % 524288
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) # 512kB OCRAM are not part of FlexRAM configurable memory
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if (
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flexram_configurable_ocram + extract_dict["dtcm_size"] + extract_dict["itcm_size"]
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) > avail_flexram:
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raise ValueError("Configuration exceeds available FlexRAM!")
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for size, pattern in (
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(flexram_configurable_ocram, "01"),
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(extract_dict["dtcm_size"], "10"),
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(extract_dict["itcm_size"], "11"),
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):
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for _ in range(0, size, extract_dict["fsl_ram_bank_size"]):
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flexram_bank_cfg += pattern
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# Generate GPR Register config
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print(".equ __iomux_gpr14_adr, 0x{:08X}".format(extract_dict["gpr_base_addr"] + 0x38))
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print(".equ __iomux_gpr16_adr, 0x{:08X}".format(extract_dict["gpr_base_addr"] + 0x40))
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print(".equ __iomux_gpr17_adr, 0x{:08X}".format(extract_dict["gpr_base_addr"] + 0x44))
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print(
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".equ __iomux_gpr17_value, 0x{:08X} /* {}k OCRAM (512k OCRAM, {}k from FlexRAM), {}k DTCM, {}k ITCM */".format(
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int(flexram_bank_cfg, 2),
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extract_dict["ocram_size"] // 1024,
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flexram_configurable_ocram // 1024,
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extract_dict["dtcm_size"] // 1024,
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extract_dict["itcm_size"] // 1024,
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)
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)
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def main(defines_file, features_file, ld_script, controller):
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dispatcher = {
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"MIMXRT1011": (mimxrt_default_parser, mimxrt_default_gen_code),
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"MIMXRT1021": (mimxrt_default_parser, mimxrt_default_gen_code),
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"MIMXRT1052": (mimxrt_default_parser, mimxrt_default_gen_code),
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"MIMXRT1062": (mimxrt_default_parser, mimxrt_106x_gen_code),
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"MIMXRT1064": (mimxrt_default_parser, mimxrt_106x_gen_code),
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}
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extractor, code_generator = dispatcher[controller]
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extract_dict = extractor(defines_file, features_file, ld_script)
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code_generator(extract_dict)
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if __name__ == "__main__":
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parser = argparse.ArgumentParser(
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prog="make-flexram-ld.py",
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usage="%(prog)s [options] [command]",
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description="Evaluate FlexRAM configuration and generate startup code.",
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)
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parser.add_argument(
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"-d",
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"--defines_file",
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dest="defines_file",
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help="Path to MCU defines file",
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default="../../../lib/nxp_driver/sdk/devices/MIMXRT1021/MIMXRT1021.h",
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)
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parser.add_argument(
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"-f",
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"--features_file",
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dest="features_file",
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help="Path to MCU features file",
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default="../../../lib/nxp_driver/sdk/devices/MIMXRT1021/MIMXRT1021_features.h",
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)
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parser.add_argument(
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"-l",
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"--ld_file",
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dest="linker_file",
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help="Path to the aggregated linker-script",
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default="MIMXRT1021.ld",
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)
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parser.add_argument(
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"-c", "--controller", dest="controller", help="Controller name", default="MIMXRT1021"
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)
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#
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args = parser.parse_args()
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main(args.defines_file, args.features_file, args.linker_file, args.controller)
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