kopia lustrzana https://github.com/micropython/micropython
320 wiersze
14 KiB
C
320 wiersze
14 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2016 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef MICROPY_INCLUDED_PY_ASMXTENSA_H
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#define MICROPY_INCLUDED_PY_ASMXTENSA_H
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#include "py/asmbase.h"
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// calling conventions:
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// up to 6 args in a2-a7
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// return value in a2
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// PC stored in a0
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// stack pointer is a1, stack full descending, is aligned to 16 bytes
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// callee save: a1, a12, a13, a14, a15
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// caller save: a3
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#define ASM_XTENSA_REG_A0 (0)
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#define ASM_XTENSA_REG_A1 (1)
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#define ASM_XTENSA_REG_A2 (2)
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#define ASM_XTENSA_REG_A3 (3)
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#define ASM_XTENSA_REG_A4 (4)
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#define ASM_XTENSA_REG_A5 (5)
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#define ASM_XTENSA_REG_A6 (6)
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#define ASM_XTENSA_REG_A7 (7)
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#define ASM_XTENSA_REG_A8 (8)
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#define ASM_XTENSA_REG_A9 (9)
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#define ASM_XTENSA_REG_A10 (10)
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#define ASM_XTENSA_REG_A11 (11)
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#define ASM_XTENSA_REG_A12 (12)
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#define ASM_XTENSA_REG_A13 (13)
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#define ASM_XTENSA_REG_A14 (14)
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#define ASM_XTENSA_REG_A15 (15)
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// for bccz
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#define ASM_XTENSA_CCZ_EQ (0)
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#define ASM_XTENSA_CCZ_NE (1)
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// for bcc and setcc
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#define ASM_XTENSA_CC_NONE (0)
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#define ASM_XTENSA_CC_EQ (1)
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#define ASM_XTENSA_CC_LT (2)
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#define ASM_XTENSA_CC_LTU (3)
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#define ASM_XTENSA_CC_ALL (4)
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#define ASM_XTENSA_CC_BC (5)
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#define ASM_XTENSA_CC_ANY (8)
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#define ASM_XTENSA_CC_NE (9)
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#define ASM_XTENSA_CC_GE (10)
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#define ASM_XTENSA_CC_GEU (11)
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#define ASM_XTENSA_CC_NALL (12)
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#define ASM_XTENSA_CC_BS (13)
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// macros for encoding instructions (little endian versions)
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#define ASM_XTENSA_ENCODE_RRR(op0, op1, op2, r, s, t) \
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((((uint32_t)op2) << 20) | (((uint32_t)op1) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0))
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#define ASM_XTENSA_ENCODE_RRI4(op0, op1, r, s, t, imm4) \
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(((imm4) << 20) | ((op1) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0))
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#define ASM_XTENSA_ENCODE_RRI8(op0, r, s, t, imm8) \
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((((uint32_t)imm8) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0))
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#define ASM_XTENSA_ENCODE_RI16(op0, t, imm16) \
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(((imm16) << 8) | ((t) << 4) | (op0))
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#define ASM_XTENSA_ENCODE_RSR(op0, op1, op2, rs, t) \
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(((op2) << 20) | ((op1) << 16) | ((rs) << 8) | ((t) << 4) | (op0))
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#define ASM_XTENSA_ENCODE_CALL(op0, n, offset) \
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(((offset) << 6) | ((n) << 4) | (op0))
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#define ASM_XTENSA_ENCODE_CALLX(op0, op1, op2, r, s, m, n) \
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((((uint32_t)op2) << 20) | (((uint32_t)op1) << 16) | ((r) << 12) | ((s) << 8) | ((m) << 6) | ((n) << 4) | (op0))
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#define ASM_XTENSA_ENCODE_BRI8(op0, r, s, m, n, imm8) \
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(((imm8) << 16) | ((r) << 12) | ((s) << 8) | ((m) << 6) | ((n) << 4) | (op0))
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#define ASM_XTENSA_ENCODE_BRI12(op0, s, m, n, imm12) \
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(((imm12) << 12) | ((s) << 8) | ((m) << 6) | ((n) << 4) | (op0))
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#define ASM_XTENSA_ENCODE_RRRN(op0, r, s, t) \
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(((r) << 12) | ((s) << 8) | ((t) << 4) | (op0))
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#define ASM_XTENSA_ENCODE_RI7(op0, s, imm7) \
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((((imm7) & 0xf) << 12) | ((s) << 8) | ((imm7) & 0x70) | (op0))
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typedef struct _asm_xtensa_t {
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mp_asm_base_t base;
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uint32_t cur_const;
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uint32_t num_const;
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uint32_t *const_table;
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uint32_t stack_adjust;
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} asm_xtensa_t;
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void asm_xtensa_end_pass(asm_xtensa_t *as);
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void asm_xtensa_entry(asm_xtensa_t *as, int num_locals);
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void asm_xtensa_exit(asm_xtensa_t *as);
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void asm_xtensa_op16(asm_xtensa_t *as, uint16_t op);
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void asm_xtensa_op24(asm_xtensa_t *as, uint32_t op);
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// raw instructions
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static inline void asm_xtensa_op_add(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 0, 8, reg_dest, reg_src_a, reg_src_b));
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}
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static inline void asm_xtensa_op_addi(asm_xtensa_t *as, uint reg_dest, uint reg_src, int imm8) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 12, reg_dest, reg_src, imm8 & 0xff));
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}
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static inline void asm_xtensa_op_and(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 0, 1, reg_dest, reg_src_a, reg_src_b));
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}
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static inline void asm_xtensa_op_bcc(asm_xtensa_t *as, uint cond, uint reg_src1, uint reg_src2, int32_t rel8) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(7, cond, reg_src1, reg_src2, rel8 & 0xff));
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}
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static inline void asm_xtensa_op_bccz(asm_xtensa_t *as, uint cond, uint reg_src, int32_t rel12) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_BRI12(6, reg_src, cond, 1, rel12 & 0xfff));
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}
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static inline void asm_xtensa_op_callx0(asm_xtensa_t *as, uint reg) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_CALLX(0, 0, 0, 0, reg, 3, 0));
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}
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static inline void asm_xtensa_op_j(asm_xtensa_t *as, int32_t rel18) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_CALL(6, 0, rel18 & 0x3ffff));
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}
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static inline void asm_xtensa_op_jx(asm_xtensa_t *as, uint reg) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_CALLX(0, 0, 0, 0, reg, 2, 2));
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}
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static inline void asm_xtensa_op_l8ui(asm_xtensa_t *as, uint reg_dest, uint reg_base, uint byte_offset) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 0, reg_base, reg_dest, byte_offset & 0xff));
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}
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static inline void asm_xtensa_op_l16ui(asm_xtensa_t *as, uint reg_dest, uint reg_base, uint half_word_offset) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 1, reg_base, reg_dest, half_word_offset & 0xff));
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}
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static inline void asm_xtensa_op_l32i(asm_xtensa_t *as, uint reg_dest, uint reg_base, uint word_offset) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 2, reg_base, reg_dest, word_offset & 0xff));
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}
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static inline void asm_xtensa_op_l32i_n(asm_xtensa_t *as, uint reg_dest, uint reg_base, uint word_offset) {
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asm_xtensa_op16(as, ASM_XTENSA_ENCODE_RRRN(8, word_offset & 0xf, reg_base, reg_dest));
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}
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static inline void asm_xtensa_op_l32r(asm_xtensa_t *as, uint reg_dest, uint32_t op_off, uint32_t dest_off) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RI16(1, reg_dest, ((dest_off - ((op_off + 3) & ~3)) >> 2) & 0xffff));
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}
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static inline void asm_xtensa_op_mov_n(asm_xtensa_t *as, uint reg_dest, uint reg_src) {
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asm_xtensa_op16(as, ASM_XTENSA_ENCODE_RRRN(13, 0, reg_src, reg_dest));
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}
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static inline void asm_xtensa_op_movi(asm_xtensa_t *as, uint reg_dest, int32_t imm12) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 10, (imm12 >> 8) & 0xf, reg_dest, imm12 & 0xff));
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}
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static inline void asm_xtensa_op_movi_n(asm_xtensa_t *as, uint reg_dest, int imm4) {
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asm_xtensa_op16(as, ASM_XTENSA_ENCODE_RI7(12, reg_dest, imm4));
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}
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static inline void asm_xtensa_op_mull(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 2, 8, reg_dest, reg_src_a, reg_src_b));
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}
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static inline void asm_xtensa_op_or(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 0, 2, reg_dest, reg_src_a, reg_src_b));
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}
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static inline void asm_xtensa_op_ret_n(asm_xtensa_t *as) {
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asm_xtensa_op16(as, ASM_XTENSA_ENCODE_RRRN(13, 15, 0, 0));
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}
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static inline void asm_xtensa_op_s8i(asm_xtensa_t *as, uint reg_src, uint reg_base, uint byte_offset) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 4, reg_base, reg_src, byte_offset & 0xff));
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}
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static inline void asm_xtensa_op_s16i(asm_xtensa_t *as, uint reg_src, uint reg_base, uint half_word_offset) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 5, reg_base, reg_src, half_word_offset & 0xff));
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}
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static inline void asm_xtensa_op_s32i(asm_xtensa_t *as, uint reg_src, uint reg_base, uint word_offset) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 6, reg_base, reg_src, word_offset & 0xff));
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}
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static inline void asm_xtensa_op_s32i_n(asm_xtensa_t *as, uint reg_src, uint reg_base, uint word_offset) {
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asm_xtensa_op16(as, ASM_XTENSA_ENCODE_RRRN(9, word_offset & 0xf, reg_base, reg_src));
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}
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static inline void asm_xtensa_op_sll(asm_xtensa_t *as, uint reg_dest, uint reg_src) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 1, 10, reg_dest, reg_src, 0));
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}
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static inline void asm_xtensa_op_sra(asm_xtensa_t *as, uint reg_dest, uint reg_src) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 1, 11, reg_dest, 0, reg_src));
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}
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static inline void asm_xtensa_op_ssl(asm_xtensa_t *as, uint reg_src) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 0, 4, 1, reg_src, 0));
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}
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static inline void asm_xtensa_op_ssr(asm_xtensa_t *as, uint reg_src) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 0, 4, 0, reg_src, 0));
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}
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static inline void asm_xtensa_op_sub(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 0, 12, reg_dest, reg_src_a, reg_src_b));
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}
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static inline void asm_xtensa_op_xor(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {
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asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 0, 3, reg_dest, reg_src_a, reg_src_b));
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}
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// convenience functions
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void asm_xtensa_j_label(asm_xtensa_t *as, uint label);
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void asm_xtensa_bccz_reg_label(asm_xtensa_t *as, uint cond, uint reg, uint label);
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void asm_xtensa_bcc_reg_reg_label(asm_xtensa_t *as, uint cond, uint reg1, uint reg2, uint label);
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void asm_xtensa_setcc_reg_reg_reg(asm_xtensa_t *as, uint cond, uint reg_dest, uint reg_src1, uint reg_src2);
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void asm_xtensa_mov_reg_i32(asm_xtensa_t *as, uint reg_dest, uint32_t i32);
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void asm_xtensa_mov_local_reg(asm_xtensa_t *as, int local_num, uint reg_src);
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void asm_xtensa_mov_reg_local(asm_xtensa_t *as, uint reg_dest, int local_num);
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void asm_xtensa_mov_reg_local_addr(asm_xtensa_t *as, uint reg_dest, int local_num);
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#if GENERIC_ASM_API
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// The following macros provide a (mostly) arch-independent API to
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// generate native code, and are used by the native emitter.
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#define ASM_WORD_SIZE (4)
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#define REG_RET ASM_XTENSA_REG_A2
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#define REG_ARG_1 ASM_XTENSA_REG_A2
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#define REG_ARG_2 ASM_XTENSA_REG_A3
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#define REG_ARG_3 ASM_XTENSA_REG_A4
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#define REG_ARG_4 ASM_XTENSA_REG_A5
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#define REG_ARG_5 ASM_XTENSA_REG_A6
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#define REG_TEMP0 ASM_XTENSA_REG_A2
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#define REG_TEMP1 ASM_XTENSA_REG_A3
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#define REG_TEMP2 ASM_XTENSA_REG_A4
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#define REG_LOCAL_1 ASM_XTENSA_REG_A12
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#define REG_LOCAL_2 ASM_XTENSA_REG_A13
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#define REG_LOCAL_3 ASM_XTENSA_REG_A14
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#define REG_LOCAL_NUM (3)
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#define ASM_T asm_xtensa_t
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#define ASM_END_PASS asm_xtensa_end_pass
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#define ASM_ENTRY asm_xtensa_entry
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#define ASM_EXIT asm_xtensa_exit
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#define ASM_JUMP asm_xtensa_j_label
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#define ASM_JUMP_IF_REG_ZERO(as, reg, label) \
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asm_xtensa_bccz_reg_label(as, ASM_XTENSA_CCZ_EQ, reg, label)
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#define ASM_JUMP_IF_REG_NONZERO(as, reg, label) \
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asm_xtensa_bccz_reg_label(as, ASM_XTENSA_CCZ_NE, reg, label)
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#define ASM_JUMP_IF_REG_EQ(as, reg1, reg2, label) \
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asm_xtensa_bcc_reg_reg_label(as, ASM_XTENSA_CC_EQ, reg1, reg2, label)
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#define ASM_CALL_IND(as, ptr, idx) \
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do { \
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asm_xtensa_mov_reg_i32(as, ASM_XTENSA_REG_A0, (uint32_t)ptr); \
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asm_xtensa_op_callx0(as, ASM_XTENSA_REG_A0); \
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} while (0)
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#define ASM_MOV_LOCAL_REG(as, local_num, reg_src) asm_xtensa_mov_local_reg((as), (local_num), (reg_src))
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#define ASM_MOV_REG_IMM(as, reg_dest, imm) asm_xtensa_mov_reg_i32((as), (reg_dest), (imm))
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#define ASM_MOV_REG_ALIGNED_IMM(as, reg_dest, imm) asm_xtensa_mov_reg_i32((as), (reg_dest), (imm))
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#define ASM_MOV_REG_LOCAL(as, reg_dest, local_num) asm_xtensa_mov_reg_local((as), (reg_dest), (local_num))
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#define ASM_MOV_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_mov_n((as), (reg_dest), (reg_src))
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#define ASM_MOV_REG_LOCAL_ADDR(as, reg_dest, local_num) asm_xtensa_mov_reg_local_addr((as), (reg_dest), (local_num))
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#define ASM_LSL_REG_REG(as, reg_dest, reg_shift) \
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do { \
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asm_xtensa_op_ssl((as), (reg_shift)); \
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asm_xtensa_op_sll((as), (reg_dest), (reg_dest)); \
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} while (0)
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#define ASM_ASR_REG_REG(as, reg_dest, reg_shift) \
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do { \
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asm_xtensa_op_ssr((as), (reg_shift)); \
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asm_xtensa_op_sra((as), (reg_dest), (reg_dest)); \
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} while (0)
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#define ASM_OR_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_or((as), (reg_dest), (reg_dest), (reg_src))
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#define ASM_XOR_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_xor((as), (reg_dest), (reg_dest), (reg_src))
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#define ASM_AND_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_and((as), (reg_dest), (reg_dest), (reg_src))
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#define ASM_ADD_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_add((as), (reg_dest), (reg_dest), (reg_src))
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#define ASM_SUB_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_sub((as), (reg_dest), (reg_dest), (reg_src))
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#define ASM_MUL_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_mull((as), (reg_dest), (reg_dest), (reg_src))
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#define ASM_LOAD_REG_REG_OFFSET(as, reg_dest, reg_base, word_offset) asm_xtensa_op_l32i_n((as), (reg_dest), (reg_base), (word_offset))
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#define ASM_LOAD8_REG_REG(as, reg_dest, reg_base) asm_xtensa_op_l8ui((as), (reg_dest), (reg_base), 0)
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#define ASM_LOAD16_REG_REG(as, reg_dest, reg_base) asm_xtensa_op_l16ui((as), (reg_dest), (reg_base), 0)
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#define ASM_LOAD32_REG_REG(as, reg_dest, reg_base) asm_xtensa_op_l32i_n((as), (reg_dest), (reg_base), 0)
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#define ASM_STORE_REG_REG_OFFSET(as, reg_dest, reg_base, word_offset) asm_xtensa_op_s32i_n((as), (reg_dest), (reg_base), (word_offset))
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#define ASM_STORE8_REG_REG(as, reg_src, reg_base) asm_xtensa_op_s8i((as), (reg_src), (reg_base), 0)
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#define ASM_STORE16_REG_REG(as, reg_src, reg_base) asm_xtensa_op_s16i((as), (reg_src), (reg_base), 0)
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#define ASM_STORE32_REG_REG(as, reg_src, reg_base) asm_xtensa_op_s32i_n((as), (reg_src), (reg_base), 0)
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#endif // GENERIC_ASM_API
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#endif // MICROPY_INCLUDED_PY_ASMXTENSA_H
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