kopia lustrzana https://github.com/micropython/micropython
195 wiersze
7.5 KiB
C
195 wiersze
7.5 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Glenn Ruben Bakke
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <arm_cmse.h>
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#include <nrf.h>
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// Secure flash 32K.
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#define SECURE_32K_FLASH_PAGE_START (0)
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#define SECURE_32K_FLASH_PAGE_END (0)
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// Non-secure flash 992K.
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#define NONSECURE_32K_FLASH_PAGE_START (1)
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#define NONSECURE_32K_FLASH_PAGE_END (31)
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// Secure RAM 64K.
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#define SECURE_8K_RAM_BLOCK_START (0)
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#define SECURE_8K_RAM_BLOCK_END (7)
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// Non-secure RAM 128K + 64K BSD lib.
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#define NONSECURE_8K_RAM_BLOCK_START (8)
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#define NONSECURE_8K_RAM_BLOCK_END (31)
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#define PERIPHERAL_ID_GET(base_addr) (((uint32_t)(base_addr) >> 12) & 0xFF)
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#if !defined(__ARM_FEATURE_CMSE)
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#pragma warning "CMSE not enabled"
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#endif
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static void configure_flash(void) {
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for (uint8_t i = SECURE_32K_FLASH_PAGE_START; i <= SECURE_32K_FLASH_PAGE_END; i++) {
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uint32_t perm = 0;
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perm |= (SPU_FLASHREGION_PERM_EXECUTE_Enable << SPU_FLASHREGION_PERM_EXECUTE_Pos);
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perm |= (SPU_FLASHREGION_PERM_WRITE_Enable << SPU_FLASHREGION_PERM_WRITE_Pos);
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perm |= (SPU_FLASHREGION_PERM_READ_Enable << SPU_FLASHREGION_PERM_READ_Pos);
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perm |= (SPU_FLASHREGION_PERM_LOCK_Locked << SPU_FLASHREGION_PERM_LOCK_Pos);
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perm |= (SPU_FLASHREGION_PERM_SECATTR_Secure << SPU_FLASHREGION_PERM_SECATTR_Pos);
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NRF_SPU_S->FLASHREGION[i].PERM = perm;
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}
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for (uint8_t i = NONSECURE_32K_FLASH_PAGE_START; i <= NONSECURE_32K_FLASH_PAGE_END; i++) {
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uint32_t perm = 0;
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perm |= (SPU_FLASHREGION_PERM_EXECUTE_Enable << SPU_FLASHREGION_PERM_EXECUTE_Pos);
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perm |= (SPU_FLASHREGION_PERM_WRITE_Enable << SPU_FLASHREGION_PERM_WRITE_Pos);
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perm |= (SPU_FLASHREGION_PERM_READ_Enable << SPU_FLASHREGION_PERM_READ_Pos);
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perm |= (SPU_FLASHREGION_PERM_LOCK_Locked << SPU_FLASHREGION_PERM_LOCK_Pos);
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perm |= (SPU_FLASHREGION_PERM_SECATTR_Non_Secure << SPU_FLASHREGION_PERM_SECATTR_Pos);
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NRF_SPU_S->FLASHREGION[i].PERM = perm;
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}
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}
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static void configure_ram(void) {
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for (uint8_t i = SECURE_8K_RAM_BLOCK_START; i <= SECURE_8K_RAM_BLOCK_END; i++) {
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uint32_t perm = 0;
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perm |= (SPU_RAMREGION_PERM_EXECUTE_Enable << SPU_RAMREGION_PERM_EXECUTE_Pos);
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perm |= (SPU_RAMREGION_PERM_WRITE_Enable << SPU_RAMREGION_PERM_WRITE_Pos);
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perm |= (SPU_RAMREGION_PERM_READ_Enable << SPU_RAMREGION_PERM_READ_Pos);
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perm |= (SPU_RAMREGION_PERM_LOCK_Locked << SPU_RAMREGION_PERM_LOCK_Pos);
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perm |= (SPU_RAMREGION_PERM_SECATTR_Secure << SPU_RAMREGION_PERM_SECATTR_Pos);
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NRF_SPU_S->RAMREGION[i].PERM = perm;
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}
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for (uint8_t i = NONSECURE_8K_RAM_BLOCK_START; i <= NONSECURE_8K_RAM_BLOCK_END; i++) {
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uint32_t perm = 0;
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perm |= (SPU_RAMREGION_PERM_EXECUTE_Enable << SPU_RAMREGION_PERM_EXECUTE_Pos);
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perm |= (SPU_RAMREGION_PERM_WRITE_Enable << SPU_RAMREGION_PERM_WRITE_Pos);
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perm |= (SPU_RAMREGION_PERM_READ_Enable << SPU_RAMREGION_PERM_READ_Pos);
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perm |= (SPU_RAMREGION_PERM_LOCK_Locked << SPU_RAMREGION_PERM_LOCK_Pos);
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perm |= (SPU_RAMREGION_PERM_SECATTR_Non_Secure << SPU_RAMREGION_PERM_SECATTR_Pos);
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NRF_SPU_S->RAMREGION[i].PERM = perm;
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}
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}
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static void peripheral_setup(uint8_t peripheral_id)
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{
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NVIC_DisableIRQ(peripheral_id);
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uint32_t perm = 0;
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perm |= (SPU_PERIPHID_PERM_PRESENT_IsPresent << SPU_PERIPHID_PERM_PRESENT_Pos);
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perm |= (SPU_PERIPHID_PERM_SECATTR_NonSecure << SPU_PERIPHID_PERM_SECATTR_Pos);
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perm |= (SPU_PERIPHID_PERM_LOCK_Locked << SPU_PERIPHID_PERM_LOCK_Pos);
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NRF_SPU_S->PERIPHID[peripheral_id].PERM = perm;
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NVIC_SetTargetState(peripheral_id);
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}
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static void configure_peripherals(void)
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{
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NRF_SPU_S->GPIOPORT[0].PERM = 0;
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peripheral_setup(PERIPHERAL_ID_GET(NRF_REGULATORS_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_CLOCK_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_UARTE0_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_UARTE1_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_UARTE2_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_UARTE3_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_SAADC_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_TIMER0_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_TIMER1_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_TIMER2_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_RTC0_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_RTC1_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_DPPIC_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_WDT_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_EGU1_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_EGU2_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_EGU3_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_EGU4_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_EGU5_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_PWM0_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_PWM1_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_PWM2_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_PWM3_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_PDM_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_I2S_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_IPC_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_FPU_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_GPIOTE1_NS));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_NVMC_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_VMC_S));
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peripheral_setup(PERIPHERAL_ID_GET(NRF_P0_NS));
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}
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typedef void __attribute__((cmse_nonsecure_call)) nsfunc(void);
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static void jump_to_non_secure(void)
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{
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TZ_SAU_Disable();
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SAU->CTRL |= SAU_CTRL_ALLNS_Msk;
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// Set NS vector table.
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uint32_t * vtor_ns = (uint32_t *)0x8000;
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SCB_NS->VTOR = (uint32_t)vtor_ns;
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// Allow for FPU to be used by NS.
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SCB->NSACR |= (1UL << SCB_NSACR_CP10_Pos) | (1UL << SCB_NSACR_CP11_Pos);
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// Set stack pointers.
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__TZ_set_MSP_NS(vtor_ns[0]);
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__TZ_set_PSP_NS(0);
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uint32_t control_ns = __TZ_get_CONTROL_NS();
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control_ns &= ~(CONTROL_SPSEL_Msk | CONTROL_nPRIV_Msk);
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__TZ_set_CONTROL_NS(control_ns);
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// Cast NS Reset_Handler to a non-secure function.
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nsfunc *fp = (nsfunc *)vtor_ns[1];
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fp = (nsfunc *)((intptr_t)(fp) & ~1);
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if (cmse_is_nsfptr(fp)) {
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__DSB();
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__ISB();
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// Jump to Non-Secure function.
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fp();
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}
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}
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int main(void) {
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configure_flash();
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configure_ram();
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configure_peripherals();
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jump_to_non_secure();
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while (1) {
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;
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}
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return 0;
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}
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void _start(void) {main();}
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