kopia lustrzana https://github.com/micropython/micropython
122 wiersze
8.1 KiB
C
122 wiersze
8.1 KiB
C
/* generated vector header file - do not edit */
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#ifndef VECTOR_DATA_H
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#define VECTOR_DATA_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Number of interrupts allocated */
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#ifndef VECTOR_DATA_IRQ_COUNT
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#define VECTOR_DATA_IRQ_COUNT (44)
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#endif
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/* ISR prototypes */
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void sci_uart_rxi_isr(void);
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void sci_uart_txi_isr(void);
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void sci_uart_tei_isr(void);
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void sci_uart_eri_isr(void);
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void rtc_alarm_periodic_isr(void);
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void rtc_carry_isr(void);
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void agt_int_isr(void);
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void r_icu_isr(void);
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void spi_rxi_isr(void);
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void spi_txi_isr(void);
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void spi_tei_isr(void);
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void spi_eri_isr(void);
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void iic_master_rxi_isr(void);
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void iic_master_txi_isr(void);
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void iic_master_tei_isr(void);
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void iic_master_eri_isr(void);
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/* Vector table allocations */
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#define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */
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#define SCI0_RXI_IRQn ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */
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#define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */
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#define SCI0_TXI_IRQn ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */
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#define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */
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#define SCI0_TEI_IRQn ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */
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#define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */
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#define SCI0_ERI_IRQn ((IRQn_Type)3) /* SCI0 ERI (Receive error) */
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#define VECTOR_NUMBER_SCI7_RXI ((IRQn_Type)4) /* SCI7 RXI (Received data full) */
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#define SCI7_RXI_IRQn ((IRQn_Type)4) /* SCI7 RXI (Received data full) */
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#define VECTOR_NUMBER_SCI7_TXI ((IRQn_Type)5) /* SCI7 TXI (Transmit data empty) */
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#define SCI7_TXI_IRQn ((IRQn_Type)5) /* SCI7 TXI (Transmit data empty) */
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#define VECTOR_NUMBER_SCI7_TEI ((IRQn_Type)6) /* SCI7 TEI (Transmit end) */
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#define SCI7_TEI_IRQn ((IRQn_Type)6) /* SCI7 TEI (Transmit end) */
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#define VECTOR_NUMBER_SCI7_ERI ((IRQn_Type)7) /* SCI7 ERI (Receive error) */
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#define SCI7_ERI_IRQn ((IRQn_Type)7) /* SCI7 ERI (Receive error) */
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#define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type)8) /* SCI9 RXI (Received data full) */
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#define SCI9_RXI_IRQn ((IRQn_Type)8) /* SCI9 RXI (Received data full) */
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#define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */
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#define SCI9_TXI_IRQn ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */
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#define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */
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#define SCI9_TEI_IRQn ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */
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#define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type)11) /* SCI9 ERI (Receive error) */
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#define SCI9_ERI_IRQn ((IRQn_Type)11) /* SCI9 ERI (Receive error) */
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#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */
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#define RTC_ALARM_IRQn ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */
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#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */
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#define RTC_PERIOD_IRQn ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */
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#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */
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#define RTC_CARRY_IRQn ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */
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#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */
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#define AGT0_INT_IRQn ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */
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#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */
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#define ICU_IRQ0_IRQn ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */
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#define VECTOR_NUMBER_ICU_IRQ1 ((IRQn_Type)17) /* ICU IRQ1 (External pin interrupt 1) */
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#define ICU_IRQ1_IRQn ((IRQn_Type)17) /* ICU IRQ1 (External pin interrupt 1) */
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#define VECTOR_NUMBER_ICU_IRQ2 ((IRQn_Type)18) /* ICU IRQ2 (External pin interrupt 2) */
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#define ICU_IRQ2_IRQn ((IRQn_Type)18) /* ICU IRQ2 (External pin interrupt 2) */
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#define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type)19) /* ICU IRQ3 (External pin interrupt 3) */
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#define ICU_IRQ3_IRQn ((IRQn_Type)19) /* ICU IRQ3 (External pin interrupt 3) */
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#define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type)20) /* ICU IRQ4 (External pin interrupt 4) */
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#define ICU_IRQ4_IRQn ((IRQn_Type)20) /* ICU IRQ4 (External pin interrupt 4) */
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#define VECTOR_NUMBER_ICU_IRQ5 ((IRQn_Type)21) /* ICU IRQ5 (External pin interrupt 5) */
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#define ICU_IRQ5_IRQn ((IRQn_Type)21) /* ICU IRQ5 (External pin interrupt 5) */
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#define VECTOR_NUMBER_ICU_IRQ6 ((IRQn_Type)22) /* ICU IRQ6 (External pin interrupt 6) */
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#define ICU_IRQ6_IRQn ((IRQn_Type)22) /* ICU IRQ6 (External pin interrupt 6) */
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#define VECTOR_NUMBER_ICU_IRQ7 ((IRQn_Type)23) /* ICU IRQ7 (External pin interrupt 7) */
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#define ICU_IRQ7_IRQn ((IRQn_Type)23) /* ICU IRQ7 (External pin interrupt 7) */
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#define VECTOR_NUMBER_ICU_IRQ8 ((IRQn_Type)24) /* ICU IRQ8 (External pin interrupt 8) */
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#define ICU_IRQ8_IRQn ((IRQn_Type)24) /* ICU IRQ8 (External pin interrupt 8) */
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#define VECTOR_NUMBER_ICU_IRQ9 ((IRQn_Type)25) /* ICU IRQ9 (External pin interrupt 9) */
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#define ICU_IRQ9_IRQn ((IRQn_Type)25) /* ICU IRQ9 (External pin interrupt 9) */
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#define VECTOR_NUMBER_ICU_IRQ10 ((IRQn_Type)26) /* ICU IRQ10 (External pin interrupt 10) */
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#define ICU_IRQ10_IRQn ((IRQn_Type)26) /* ICU IRQ10 (External pin interrupt 10) */
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#define VECTOR_NUMBER_ICU_IRQ11 ((IRQn_Type)27) /* ICU IRQ11 (External pin interrupt 11) */
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#define ICU_IRQ11_IRQn ((IRQn_Type)27) /* ICU IRQ11 (External pin interrupt 11) */
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#define VECTOR_NUMBER_ICU_IRQ12 ((IRQn_Type)28) /* ICU IRQ12 (External pin interrupt 12) */
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#define ICU_IRQ12_IRQn ((IRQn_Type)28) /* ICU IRQ12 (External pin interrupt 12) */
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#define VECTOR_NUMBER_ICU_IRQ13 ((IRQn_Type)29) /* ICU IRQ13 (External pin interrupt 13) */
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#define ICU_IRQ13_IRQn ((IRQn_Type)29) /* ICU IRQ13 (External pin interrupt 13) */
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#define VECTOR_NUMBER_ICU_IRQ14 ((IRQn_Type)30) /* ICU IRQ14 (External pin interrupt 14) */
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#define ICU_IRQ14_IRQn ((IRQn_Type)30) /* ICU IRQ14 (External pin interrupt 14) */
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#define VECTOR_NUMBER_ICU_IRQ15 ((IRQn_Type)31) /* ICU IRQ15 (External pin interrupt 15) */
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#define ICU_IRQ15_IRQn ((IRQn_Type)31) /* ICU IRQ15 (External pin interrupt 15) */
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#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)32) /* SPI0 RXI (Receive buffer full) */
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#define SPI0_RXI_IRQn ((IRQn_Type)32) /* SPI0 RXI (Receive buffer full) */
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#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)33) /* SPI0 TXI (Transmit buffer empty) */
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#define SPI0_TXI_IRQn ((IRQn_Type)33) /* SPI0 TXI (Transmit buffer empty) */
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#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)34) /* SPI0 TEI (Transmission complete event) */
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#define SPI0_TEI_IRQn ((IRQn_Type)34) /* SPI0 TEI (Transmission complete event) */
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#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)35) /* SPI0 ERI (Error) */
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#define SPI0_ERI_IRQn ((IRQn_Type)35) /* SPI0 ERI (Error) */
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#define VECTOR_NUMBER_SPI1_RXI ((IRQn_Type)36) /* SPI1 RXI (Receive buffer full) */
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#define SPI1_RXI_IRQn ((IRQn_Type)36) /* SPI1 RXI (Receive buffer full) */
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#define VECTOR_NUMBER_SPI1_TXI ((IRQn_Type)37) /* SPI1 TXI (Transmit buffer empty) */
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#define SPI1_TXI_IRQn ((IRQn_Type)37) /* SPI1 TXI (Transmit buffer empty) */
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#define VECTOR_NUMBER_SPI1_TEI ((IRQn_Type)38) /* SPI1 TEI (Transmission complete event) */
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#define SPI1_TEI_IRQn ((IRQn_Type)38) /* SPI1 TEI (Transmission complete event) */
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#define VECTOR_NUMBER_SPI1_ERI ((IRQn_Type)39) /* SPI1 ERI (Error) */
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#define SPI1_ERI_IRQn ((IRQn_Type)39) /* SPI1 ERI (Error) */
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#define VECTOR_NUMBER_IIC2_RXI ((IRQn_Type)40) /* IIC2 RXI (Receive data full) */
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#define IIC2_RXI_IRQn ((IRQn_Type)40) /* IIC2 RXI (Receive data full) */
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#define VECTOR_NUMBER_IIC2_TXI ((IRQn_Type)41) /* IIC2 TXI (Transmit data empty) */
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#define IIC2_TXI_IRQn ((IRQn_Type)41) /* IIC2 TXI (Transmit data empty) */
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#define VECTOR_NUMBER_IIC2_TEI ((IRQn_Type)42) /* IIC2 TEI (Transmit end) */
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#define IIC2_TEI_IRQn ((IRQn_Type)42) /* IIC2 TEI (Transmit end) */
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#define VECTOR_NUMBER_IIC2_ERI ((IRQn_Type)43) /* IIC2 ERI (Transfer error) */
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#define IIC2_ERI_IRQn ((IRQn_Type)43) /* IIC2 ERI (Transfer error) */
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#ifdef __cplusplus
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}
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#endif
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#endif /* VECTOR_DATA_H */
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