kopia lustrzana https://github.com/micropython/micropython
163 wiersze
7.0 KiB
C
163 wiersze
7.0 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2023 NXP
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. Setup clock sources.
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*
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* 2. Set up wait states of the flash.
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*
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* 3. Set up all dividers.
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*
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* 4. Set up all selectors to provide selected clocks.
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*
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*/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v12.0
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processor: MCXN947
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package_id: MCXN947VDF
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mcu_data: ksdk2_0
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processor_version: 0.14.14
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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#include "fsl_clock.h"
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#include "clock_config.h"
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#include "fsl_spc.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void) {
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BOARD_BootClockPLL150M();
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockPLL150M *********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockPLL150M
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called_from_default_init: true
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outputs:
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- {id: CLK_144M_clock.outFreq, value: 144 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: FRO_HF_clock.outFreq, value: 48 MHz}
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- {id: MAIN_clock.outFreq, value: 150 MHz}
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- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
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- {id: Slow_clock.outFreq, value: 37.5 MHz}
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- {id: System_clock.outFreq, value: 150 MHz}
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- {id: gdet_clock.outFreq, value: 48 MHz}
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- {id: trng_clock.outFreq, value: 48 MHz}
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settings:
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- {id: PLL0_Mode, value: Normal}
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- {id: RunPowerMode, value: OD}
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- {id: SCGMode, value: PLL0}
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- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
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- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
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- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
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- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
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- {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
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- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
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- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockPLL150M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockPLL150M configuration
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******************************************************************************/
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void BOARD_BootClockPLL150M(void) {
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CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */
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/* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */
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/* Set the DCDC VDD regulator to 1.2 V voltage level */
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spc_active_mode_dcdc_option_t dcdcOpt = {
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.DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
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.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
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};
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SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt);
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/* Set the LDO_CORE VDD regulator to 1.2 V voltage level */
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spc_active_mode_core_ldo_option_t ldoOpt = {
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.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
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.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
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};
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SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt);
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/* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */;
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FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));
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/* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */
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spc_sram_voltage_config_t sramCfg = {
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.operateVoltage = kSPC_sramOperateAt1P2V,
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.requestVoltageUpdate = true,
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};
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SPC_SetSRAMOperateVoltage(SPC0, &sramCfg);
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CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
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/*!< Set up PLL0 */
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const pll_setup_t pll0Setup = {
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.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
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.pllndiv = SCG_APLLNDIV_NDIV(8U),
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.pllpdiv = SCG_APLLPDIV_PDIV(1U),
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.pllmdiv = SCG_APLLMDIV_MDIV(50U),
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.pllRate = 150000000U
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};
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CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
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CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */
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/*!< Set up clock selectors */
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CLOCK_AttachClk(kPLL0_to_MAIN_CLK);
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
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}
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