kopia lustrzana https://github.com/micropython/micropython
76cf98c35b
By using the phase jitter between the DFLL48M clock and the FDPLL96M clock. Even if both use the same reference source, they have a different jitter. SysTick is driven by FDPLL96M, the us counter by DFLL48M. As a random source, the us counter is read out on every SysTick and the value is used to accumulate a simple multiply, add and xor register. According to tests it creates about 30 bit random bit-flips per second. That mechanism will pass quite a few RNG tests, has a suitable frequency distribution and serves better than just the time after boot to seed the PRNG. |
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| tutorial | ||
| general.rst | ||
| pinout.rst | ||
| quickref.rst | ||