kopia lustrzana https://github.com/micropython/micropython
1522 wiersze
38 KiB
C
1522 wiersze
38 KiB
C
//*****************************************************************************
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//
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// spi.c
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//
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// Driver for the SPI.
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup SPI_Serial_Peripheral_Interface_api
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_ints.h"
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#include "inc/hw_types.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_mcspi.h"
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#include "inc/hw_apps_config.h"
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#include "interrupt.h"
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#include "spi.h"
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//*****************************************************************************
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//
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// A mapping of SPI base address to interupt number.
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//
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//*****************************************************************************
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static const unsigned long g_ppulSPIIntMap[][3] =
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{
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{ SSPI_BASE, INT_SSPI }, // Shared SPI
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{ GSPI_BASE, INT_GSPI }, // Generic SPI
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{ LSPI_BASE, INT_LSPI }, // LINK SPI
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};
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//*****************************************************************************
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//
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// A mapping of SPI base address to DMA done interrupt mask bit(s).
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//
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//*****************************************************************************
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static const unsigned long g_ulSPIDmaMaskMap[][2]=
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{
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{SSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK},
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{LSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK},
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{GSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK},
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};
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//*****************************************************************************
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//
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//! \internal
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//! Transfer bytes over SPI channel
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//!
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//! \param ulBase is the base address of SPI module
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//! \param ucDout is the pointer to Tx data buffer or 0.
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//! \param ucDin is pointer to Rx data buffer or 0
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//! \param ulCount is the size of data in bytes.
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//!
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//! This function transfers \e ulCount bytes of data over SPI channel.
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//!
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//! The function will not return until data has been transmitted
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//!
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//! \return Returns 0 on success, -1 otherwise.
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//
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//*****************************************************************************
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static long SPITransfer8(unsigned long ulBase, unsigned char *ucDout,
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unsigned char *ucDin, unsigned long ulCount,
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unsigned long ulFlags)
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{
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unsigned long ulReadReg;
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unsigned long ulWriteReg;
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unsigned long ulStatReg;
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unsigned long ulOutIncr;
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unsigned long ulInIncr;
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unsigned long ulTxDummy;
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unsigned long ulRxDummy;
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//
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// Initialize the variables
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//
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ulOutIncr = 1;
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ulInIncr = 1;
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//
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// Check if output buffer pointer is 0
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//
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if(ucDout == 0)
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{
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ulOutIncr = 0;
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ulTxDummy = 0xFFFFFFFF;
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ucDout = (unsigned char *)&ulTxDummy;
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}
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//
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// Check if input buffer pointer is 0
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//
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if(ucDin == 0)
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{
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ulInIncr = 0;
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ucDin = (unsigned char *)&ulRxDummy;
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}
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//
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// Load the register addresses.
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//
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ulReadReg = (ulBase + MCSPI_O_RX0);
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ulWriteReg = (ulBase + MCSPI_O_TX0);
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ulStatReg = (ulBase + MCSPI_O_CH0STAT);
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//
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// Enable CS based on Flag
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//
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if( ulFlags & SPI_CS_ENABLE)
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{
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HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;
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}
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while(ulCount)
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{
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//
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// Wait for space in output register/FIFO.
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//
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while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) )
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{
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}
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//
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// Write the data
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//
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HWREG(ulWriteReg) = *ucDout;
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//
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// Wait for data in input register/FIFO.
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//
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while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) )
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{
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}
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//
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// Read the data
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//
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*ucDin = HWREG(ulReadReg);
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//
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// Increment pointers.
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//
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ucDout = ucDout + ulOutIncr;
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ucDin = ucDin + ulInIncr;
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//
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// Decrement the count.
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//
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ulCount--;
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}
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//
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// Disable CS based on Flag
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//
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if( ulFlags & SPI_CS_DISABLE)
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{
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HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;
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}
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return 0;
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}
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//*****************************************************************************
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//
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//! \internal
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//! Transfer half-words over SPI channel
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//!
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//! \param ulBase is the base address of SPI module
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//! \param usDout is the pointer to Tx data buffer or 0.
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//! \param usDin is pointer to Rx data buffer or 0
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//! \param ulCount is the size of data in bytes.
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//!
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//! This function transfers \e ulCount bytes of data over SPI channel. Since
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//! the API sends a half-word at a time \e ulCount should be a multiple
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//! of two.
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//!
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//! The function will not return until data has been transmitted
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//!
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//! \return Returns 0 on success, -1 otherwise.
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//
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//*****************************************************************************
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static long SPITransfer16(unsigned long ulBase, unsigned short *usDout,
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unsigned short *usDin, unsigned long ulCount,
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unsigned long ulFlags)
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{
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unsigned long ulReadReg;
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unsigned long ulWriteReg;
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unsigned long ulStatReg;
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unsigned long ulOutIncr;
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unsigned long ulInIncr;
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unsigned long ulTxDummy;
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unsigned long ulRxDummy;
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//
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// Initialize the variables.
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//
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ulOutIncr = 1;
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ulInIncr = 1;
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//
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// Check if count is multiple of half-word
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//
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if(ulCount%2)
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{
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return -1;
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}
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//
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// Compute number of half words.
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//
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ulCount = ulCount/2;
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//
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// Check if output buffer pointer is 0
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//
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if(usDout == 0)
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{
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ulOutIncr = 0;
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ulTxDummy = 0xFFFFFFFF;
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usDout = (unsigned short *)&ulTxDummy;
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}
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//
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// Check if input buffer pointer is 0
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//
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if(usDin == 0)
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{
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ulInIncr = 0;
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usDin = (unsigned short *)&ulRxDummy;
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}
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//
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// Load the register addresses.
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//
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ulReadReg = (ulBase + MCSPI_O_RX0);
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ulWriteReg = (ulBase + MCSPI_O_TX0);
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ulStatReg = (ulBase + MCSPI_O_CH0STAT);
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//
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// Enable CS based on Flag
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//
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if( ulFlags & SPI_CS_ENABLE)
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{
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HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;
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}
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while(ulCount)
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{
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//
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// Wait for space in output register/FIFO.
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//
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while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) )
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{
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}
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//
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// Write the data
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//
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HWREG(ulWriteReg) = *usDout;
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//
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// Wait for data in input register/FIFO.
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//
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while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) )
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{
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}
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//
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// Read the data
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//
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*usDin = HWREG(ulReadReg);
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//
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// Increment pointers.
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//
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usDout = usDout + ulOutIncr;
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usDin = usDin + ulInIncr;
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//
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// Decrement the count.
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//
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ulCount--;
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}
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//
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// Disable CS based on Flag
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//
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if( ulFlags & SPI_CS_DISABLE)
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{
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HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;
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}
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return 0;
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}
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//*****************************************************************************
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//
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//! \internal
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//! Transfer words over SPI channel
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//!
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//! \param ulBase is the base address of SPI module
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//! \param ulDout is the pointer to Tx data buffer or 0.
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//! \param ulDin is pointer to Rx data buffer or 0
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//! \param ulCount is the size of data in bytes.
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//!
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//! This function transfers \e ulCount bytes of data over SPI channel. Since
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//! the API sends a word at a time \e ulCount should be a multiple of four.
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//!
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//! The function will not return until data has been transmitted
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//!
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//! \return Returns 0 on success, -1 otherwise.
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//
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//*****************************************************************************
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static long SPITransfer32(unsigned long ulBase, unsigned long *ulDout,
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unsigned long *ulDin, unsigned long ulCount,
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unsigned long ulFlags)
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{
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unsigned long ulReadReg;
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unsigned long ulWriteReg;
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unsigned long ulStatReg;
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unsigned long ulOutIncr;
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unsigned long ulInIncr;
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unsigned long ulTxDummy;
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unsigned long ulRxDummy;
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//
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// Initialize the variables.
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//
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ulOutIncr = 1;
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ulInIncr = 1;
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//
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// Check if count is multiple of word
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//
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if(ulCount%4)
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{
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return -1;
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}
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//
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// Compute the number of words to be transferd
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//
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ulCount = ulCount/4;
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//
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// Check if output buffer pointer is 0
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//
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if(ulDout == 0)
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{
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ulOutIncr = 0;
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ulTxDummy = 0xFFFFFFFF;
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ulDout = &ulTxDummy;
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}
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//
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// Check if input buffer pointer is 0
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//
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if(ulDin == 0)
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{
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ulInIncr = 0;
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ulDin = &ulRxDummy;
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}
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//
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// Load the register addresses.
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//
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ulReadReg = (ulBase + MCSPI_O_RX0);
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ulWriteReg = (ulBase + MCSPI_O_TX0);
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ulStatReg = (ulBase + MCSPI_O_CH0STAT);
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//
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// Enable CS based on Flag
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//
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if( ulFlags & SPI_CS_ENABLE)
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{
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HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;
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}
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while(ulCount)
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{
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//
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// Wait for space in output register/FIFO.
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//
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while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) )
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{
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}
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//
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// Write the data
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//
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HWREG(ulWriteReg) = *ulDout;
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//
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// Wait for data in input register/FIFO.
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//
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while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) )
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{
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}
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//
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// Read the data
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//
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*ulDin = HWREG(ulReadReg);
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//
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// Increment pointers.
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//
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ulDout = ulDout + ulOutIncr;
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ulDin = ulDin + ulInIncr;
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//
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// Decrement the count.
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//
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ulCount--;
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}
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//
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// Disable CS based on Flag
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//
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if( ulFlags & SPI_CS_DISABLE)
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{
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HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;
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}
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return 0;
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}
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//*****************************************************************************
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//
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//! \internal
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//! Gets the SPI interrupt number.
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//!
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//! \param ulBase is the base address of the SPI module
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//!
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//! Given a SPI base address, returns the corresponding interrupt number.
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//!
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//! \return Returns a SPI interrupt number, or -1 if \e ulBase is invalid.
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//
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//*****************************************************************************
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static long
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SPIIntNumberGet(unsigned long ulBase)
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{
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unsigned long ulIdx;
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//
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// Loop through the table that maps SPI base addresses to interrupt
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// numbers.
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//
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for(ulIdx = 0; ulIdx < (sizeof(g_ppulSPIIntMap) /
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sizeof(g_ppulSPIIntMap[0])); ulIdx++)
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{
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//
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// See if this base address matches.
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//
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if(g_ppulSPIIntMap[ulIdx][0] == ulBase)
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{
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//
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// Return the corresponding interrupt number.
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//
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return(g_ppulSPIIntMap[ulIdx][1]);
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}
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}
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//
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// The base address could not be found, so return an error.
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//
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return(-1);
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}
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//*****************************************************************************
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//
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//! \internal
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//! Gets the SPI DMA interrupt mask bit.
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//!
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//! \param ulBase is the base address of the SPI module
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//!
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//! Given a SPI base address, DMA interrupt mask bit.
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//!
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//! \return Returns a DMA interrupt mask bit, or -1 if \e ulBase is invalid.
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//
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//*****************************************************************************
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static long
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SPIDmaMaskGet(unsigned long ulBase)
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{
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unsigned long ulIdx;
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|
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//
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// Loop through the table that maps SPI base addresses to interrupt
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// numbers.
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//
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for(ulIdx = 0; ulIdx < (sizeof(g_ulSPIDmaMaskMap) /
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sizeof(g_ulSPIDmaMaskMap[0])); ulIdx++)
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{
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//
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// See if this base address matches.
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//
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if(g_ulSPIDmaMaskMap[ulIdx][0] == ulBase)
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{
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//
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// Return the corresponding interrupt number.
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//
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return(g_ulSPIDmaMaskMap[ulIdx][1]);
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}
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}
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//
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// The base address could not be found, so return an error.
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//
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return(-1);
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}
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//*****************************************************************************
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//
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//! Enables transmitting and receiving.
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//!
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//! \param ulBase is the base address of the SPI module
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//!
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//! This function enables the SPI channel for transmitting and receiving.
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//!
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//! \return None
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//!
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//
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//*****************************************************************************
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void
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SPIEnable(unsigned long ulBase)
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{
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//
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// Set Channel Enable Bit
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//
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HWREG(ulBase + MCSPI_O_CH0CTRL) |= MCSPI_CH0CTRL_EN;
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}
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|
|
//*****************************************************************************
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//
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//! Disables the transmitting and receiving.
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//!
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//! \param ulBase is the base address of the SPI module
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//!
|
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//! This function disables the SPI channel for transmitting and receiving.
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//!
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//! \return None
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//!
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//
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//*****************************************************************************
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void
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SPIDisable(unsigned long ulBase)
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{
|
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//
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// Reset Channel Enable Bit
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//
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HWREG(ulBase + MCSPI_O_CH0CTRL) &= ~MCSPI_CH0CTRL_EN;
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}
|
|
|
|
|
|
//*****************************************************************************
|
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//
|
|
//! Enables the SPI DMA operation for transmitting and/or receving.
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|
//!
|
|
//! \param ulBase is the base address of the SPI module
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|
//! \param ulFlags selectes the DMA signal for transmit and/or receive.
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|
//!
|
|
//! This function enables transmit and/or receive DMA request based on the
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//! \e ulFlags parameter.
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|
//!
|
|
//! The parameter \e ulFlags is the logical OR of one or more of
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|
//! the following :
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//! - \b SPI_RX_DMA
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|
//! - \b SPI_TX_DMA
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|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags)
|
|
{
|
|
//
|
|
// Enable DMA based on ulFlags
|
|
//
|
|
HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables the SPI DMA operation for transmitting and/or receving.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param ulFlags selectes the DMA signal for transmit and/or receive.
|
|
//!
|
|
//! This function disables transmit and/or receive DMA request based on the
|
|
//! \e ulFlags parameter.
|
|
//!
|
|
//! The parameter \e ulFlags is the logical OR of one or more of
|
|
//! the following :
|
|
//! - \b SPI_RX_DMA
|
|
//! - \b SPI_TX_DMA
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags)
|
|
{
|
|
//
|
|
// Disable DMA based on ulFlags
|
|
//
|
|
HWREG(ulBase + MCSPI_O_CH0CONF) &= ulFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Performs a software reset of the specified SPI module
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//!
|
|
//! This function performs a software reset of the specified SPI module
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIReset(unsigned long ulBase)
|
|
{
|
|
|
|
//
|
|
// Assert soft reset (auto clear)
|
|
//
|
|
HWREG(ulBase + MCSPI_O_SYSCONFIG) |= MCSPI_SYSCONFIG_SOFTRESET;
|
|
|
|
//
|
|
// wait until reset is done
|
|
//
|
|
while(!(HWREG(ulBase + MCSPI_O_SYSSTATUS)& MCSPI_SYSSTATUS_RESETDONE))
|
|
{
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the configuration of a SPI module
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param ulSPIClk is the rate of clock supplied to the SPI module.
|
|
//! \param ulBitRate is the desired bit rate.(master mode)
|
|
//! \param ulMode is the mode of operation.
|
|
//! \param ulSubMode is one of the valid sub-modes.
|
|
//! \param ulConfig is logical OR of configuration paramaters.
|
|
//!
|
|
//! This function configures SPI port for operation in specified sub-mode and
|
|
//! required bit rated as specified by \e ulMode and \e ulBitRate parameters
|
|
//! respectively.
|
|
//!
|
|
//! The SPI module can operate in either master or slave mode. The parameter
|
|
//! \e ulMode can be one of the following
|
|
//! -\b SPI_MODE_MASTER
|
|
//! -\b SPI_MODE_SLAVE
|
|
//!
|
|
//! The SPI module supports 4 sub modes based on SPI clock polarity and phase.
|
|
//!
|
|
//! <pre>
|
|
//! Polarity Phase Sub-Mode
|
|
//! 0 0 0
|
|
//! 0 1 1
|
|
//! 1 0 2
|
|
//! 1 1 3
|
|
//! </pre>
|
|
//!
|
|
//! Required sub mode can be select by setting \e ulSubMode parameter to one
|
|
//! of the following
|
|
//! - \b SPI_SUB_MODE_0
|
|
//! - \b SPI_SUB_MODE_1
|
|
//! - \b SPI_SUB_MODE_2
|
|
//! - \b SPI_SUB_MODE_3
|
|
//!
|
|
//! The parameter \e ulConfig is logical OR of five values: the word length,
|
|
//! active level for chip select, software or hardware controled chip select,
|
|
//! 3 or 4 pin mode and turbo mode.
|
|
//! mode.
|
|
//!
|
|
//! SPI support 8, 16 and 32 bit word lengths defined by:-
|
|
//! - \b SPI_WL_8
|
|
//! - \b SPI_WL_16
|
|
//! - \b SPI_WL_32
|
|
//!
|
|
//! Active state of Chip Select can be defined by:-
|
|
//! - \b SPI_CS_ACTIVELOW
|
|
//! - \b SPI_CS_ACTIVEHIGH
|
|
//!
|
|
//! SPI chip select can be configured to be controlled either by hardware or
|
|
//! software:-
|
|
//! - \b SPI_SW_CS
|
|
//! - \b SPI_HW_CS
|
|
//!
|
|
//! The module can work in 3 or 4 pin mode defined by:-
|
|
//! - \b SPI_3PIN_MODE
|
|
//! - \b SPI_4PIN_MODE
|
|
//!
|
|
//! Turbo mode can be set on or turned off using:-
|
|
//! - \b SPI_TURBO_MODE_ON
|
|
//! - \b SPI_TURBO_MODE_OFF
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,
|
|
unsigned long ulBitRate, unsigned long ulMode,
|
|
unsigned long ulSubMode, unsigned long ulConfig)
|
|
{
|
|
|
|
unsigned long ulRegData;
|
|
unsigned long ulDivider;
|
|
|
|
//
|
|
// Read MODULCTRL register
|
|
//
|
|
ulRegData = HWREG(ulBase + MCSPI_O_MODULCTRL);
|
|
|
|
//
|
|
// Set Master mode with h/w chip select
|
|
//
|
|
ulRegData &= ~(MCSPI_MODULCTRL_MS |
|
|
MCSPI_MODULCTRL_SINGLE);
|
|
|
|
//
|
|
// Enable software control Chip Select, Init delay
|
|
// and 3-pin mode
|
|
//
|
|
ulRegData |= (((ulConfig >> 24) | ulMode) & 0xFF);
|
|
|
|
//
|
|
// Write the configuration
|
|
//
|
|
HWREG(ulBase + MCSPI_O_MODULCTRL) = ulRegData;
|
|
|
|
//
|
|
// Set IS, DPE0, DPE1 based on master or slave mode
|
|
//
|
|
if(ulMode == SPI_MODE_MASTER)
|
|
{
|
|
ulRegData = 0x1 << 16;
|
|
}
|
|
else
|
|
{
|
|
ulRegData = 0x6 << 16;
|
|
}
|
|
|
|
//
|
|
// set clock divider granularity to 1 cycle
|
|
//
|
|
ulRegData |= MCSPI_CH0CONF_CLKG;
|
|
|
|
//
|
|
// Get the divider value
|
|
//
|
|
ulDivider = ((ulSPIClk/ulBitRate) - 1);
|
|
|
|
//
|
|
// The least significant four bits of the divider is used to configure
|
|
// CLKD in MCSPI_CHCONF next eight least significant bits are used to
|
|
// configure the EXTCLK in MCSPI_CHCTRL
|
|
//
|
|
ulRegData |= ((ulDivider & 0x0000000F) << 2);
|
|
HWREG(ulBase + MCSPI_O_CH0CTRL) = ((ulDivider & 0x00000FF0) << 4);
|
|
|
|
//
|
|
// Set the protocol, CS polarity, word length
|
|
// and turbo mode
|
|
//
|
|
ulRegData = ((ulRegData |
|
|
ulSubMode) | (ulConfig & 0x0008FFFF));
|
|
|
|
//
|
|
// Write back the CONF register
|
|
//
|
|
HWREG(ulBase + MCSPI_O_CH0CONF) = ulRegData;
|
|
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Receives a word from the specified port.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module.
|
|
//! \param pulData is pointer to receive data variable.
|
|
//!
|
|
//! This function gets a SPI word from the receive FIFO for the specified
|
|
//! port.
|
|
//!
|
|
//! \return Returns the number of elements read from the receive FIFO.
|
|
//
|
|
//*****************************************************************************
|
|
long
|
|
SPIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
|
|
{
|
|
unsigned long ulRegVal;
|
|
|
|
//
|
|
// Read register status register
|
|
//
|
|
ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT);
|
|
|
|
//
|
|
// Check is data is available
|
|
//
|
|
if(ulRegVal & MCSPI_CH0STAT_RXS)
|
|
{
|
|
*pulData = HWREG(ulBase + MCSPI_O_RX0);
|
|
return(1);
|
|
}
|
|
|
|
return(0);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Waits for the word to be received on the specified port.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module.
|
|
//! \param pulData is pointer to receive data variable.
|
|
//!
|
|
//! This function gets a SPI word from the receive FIFO for the specified
|
|
//! port. If there is no word available, this function waits until a
|
|
//! word is received before returning.
|
|
//!
|
|
//! \return Returns the word read from the specified port, cast as an
|
|
//! \e unsigned long.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIDataGet(unsigned long ulBase, unsigned long *pulData)
|
|
{
|
|
//
|
|
// Wait for Rx data
|
|
//
|
|
while(!(HWREG(ulBase + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_RXS))
|
|
{
|
|
}
|
|
|
|
//
|
|
// Read the value
|
|
//
|
|
*pulData = HWREG(ulBase + MCSPI_O_RX0);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Transmits a word on the specified port.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param ulData is data to be transmitted.
|
|
//!
|
|
//! This function transmits a SPI word on the transmit FIFO for the specified
|
|
//! port.
|
|
//!
|
|
//! \return Returns the number of elements written to the transmit FIFO.
|
|
//!
|
|
//*****************************************************************************
|
|
long
|
|
SPIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
|
|
{
|
|
unsigned long ulRegVal;
|
|
|
|
//
|
|
// Read status register
|
|
//
|
|
ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT);
|
|
|
|
//
|
|
// Write value into Tx register/FIFO
|
|
// if space is available
|
|
//
|
|
if(ulRegVal & MCSPI_CH0STAT_TXS)
|
|
{
|
|
HWREG(ulBase + MCSPI_O_TX0) = ulData;
|
|
return(1);
|
|
}
|
|
|
|
return(0);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Waits until the word is transmitted on the specified port.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param ulData is data to be transmitted.
|
|
//!
|
|
//! This function transmits a SPI word on the transmit FIFO for the specified
|
|
//! port. This function waits until the space is available on transmit FIFO
|
|
//!
|
|
//! \return None
|
|
//!
|
|
//*****************************************************************************
|
|
void
|
|
SPIDataPut(unsigned long ulBase, unsigned long ulData)
|
|
{
|
|
//
|
|
// Wait for space in FIFO
|
|
//
|
|
while(!(HWREG(ulBase + MCSPI_O_CH0STAT)&MCSPI_CH0STAT_TXS))
|
|
{
|
|
}
|
|
|
|
//
|
|
// Write the data
|
|
//
|
|
HWREG(ulBase + MCSPI_O_TX0) = ulData;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables the transmit and/or receive FIFOs.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param ulFlags selects the FIFO(s) to be enabled
|
|
//!
|
|
//! This function enables the transmit and/or receive FIFOs as specified by
|
|
//! \e ulFlags.
|
|
//! The parameter \e ulFlags shoulde be logical OR of one or more of the
|
|
//! following:
|
|
//! - \b SPI_TX_FIFO
|
|
//! - \b SPI_RX_FIFO
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags)
|
|
{
|
|
//
|
|
// Set FIFO enable bits.
|
|
//
|
|
HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables the transmit and/or receive FIFOs.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param ulFlags selects the FIFO(s) to be enabled
|
|
//!
|
|
//! This function disables transmit and/or receive FIFOs. as specified by
|
|
//! \e ulFlags.
|
|
//! The parameter \e ulFlags shoulde be logical OR of one or more of the
|
|
//! following:
|
|
//! - \b SPI_TX_FIFO
|
|
//! - \b SPI_RX_FIFO
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags)
|
|
{
|
|
//
|
|
// Reset FIFO Enable bits.
|
|
//
|
|
HWREG(ulBase + MCSPI_O_CH0CONF) &= ~(ulFlags);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the FIFO level at which DMA requests or interrupts are generated.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param ulTxLevel is the Almost Empty Level for transmit FIFO.
|
|
//! \param ulRxLevel is the Almost Full Level for the receive FIFO.
|
|
//!
|
|
//! This function Sets the FIFO level at which DMA requests or interrupts
|
|
//! are generated.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
|
|
unsigned long ulRxLevel)
|
|
{
|
|
unsigned long ulRegVal;
|
|
|
|
//
|
|
// Read the current configuration
|
|
//
|
|
ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL);
|
|
|
|
//
|
|
// Mask and set new FIFO thresholds.
|
|
//
|
|
ulRegVal = ((ulRegVal & 0xFFFF0000) | (((ulRxLevel-1) << 8) | (ulTxLevel-1)));
|
|
|
|
//
|
|
// Set the transmit and receive FIFO thresholds.
|
|
//
|
|
HWREG(ulBase + MCSPI_O_XFERLEVEL) = ulRegVal;
|
|
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the FIFO level at which DMA requests or interrupts are generated.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param pulTxLevel is a pointer to storage for the transmit FIFO level
|
|
//! \param pulRxLevel is a pointer to storage for the receive FIFO level
|
|
//!
|
|
//! This function gets the FIFO level at which DMA requests or interrupts
|
|
//! are generated.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
|
|
unsigned long *pulRxLevel)
|
|
{
|
|
unsigned long ulRegVal;
|
|
|
|
//
|
|
// Read the current configuration
|
|
//
|
|
ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL);
|
|
|
|
*pulTxLevel = (ulRegVal & 0xFF);
|
|
|
|
*pulRxLevel = ((ulRegVal >> 8) & 0xFF);
|
|
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the word count.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param ulWordCount is number of SPI words to be transmitted.
|
|
//!
|
|
//! This function sets the word count, which is the number of SPI word to
|
|
//! be transferred on channel when using the FIFO buffer.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount)
|
|
{
|
|
unsigned long ulRegVal;
|
|
|
|
//
|
|
// Read the current configuration
|
|
//
|
|
ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL);
|
|
|
|
//
|
|
// Mask and set the word count
|
|
//
|
|
HWREG(ulBase + MCSPI_O_XFERLEVEL) = ((ulRegVal & 0x0000FFFF)|
|
|
(ulWordCount & 0xFFFF) << 16);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Registers an interrupt handler for a SPI interrupt.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param pfnHandler is a pointer to the function to be called when the
|
|
//! SPI interrupt occurs.
|
|
//!
|
|
//! This function does the actual registering of the interrupt handler. This
|
|
//! function enables the global interrupt in the interrupt controller; specific
|
|
//! SPI interrupts must be enabled via SPIIntEnable(). It is the interrupt
|
|
//! handler's responsibility to clear the interrupt source.
|
|
//!
|
|
//! \sa IntRegister() for important information about registering interrupt
|
|
//! handlers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void))
|
|
{
|
|
unsigned long ulInt;
|
|
|
|
//
|
|
// Determine the interrupt number based on the SPI module
|
|
//
|
|
ulInt = SPIIntNumberGet(ulBase);
|
|
|
|
//
|
|
// Register the interrupt handler.
|
|
//
|
|
IntRegister(ulInt, pfnHandler);
|
|
|
|
//
|
|
// Enable the SPI interrupt.
|
|
//
|
|
IntEnable(ulInt);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Unregisters an interrupt handler for a SPI interrupt.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//!
|
|
//! This function does the actual unregistering of the interrupt handler. It
|
|
//! clears the handler to be called when a SPI interrupt occurs. This
|
|
//! function also masks off the interrupt in the interrupt controller so that
|
|
//! the interrupt handler no longer is called.
|
|
//!
|
|
//! \sa IntRegister() for important information about registering interrupt
|
|
//! handlers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIIntUnregister(unsigned long ulBase)
|
|
{
|
|
unsigned long ulInt;
|
|
|
|
//
|
|
// Determine the interrupt number based on the SPI module
|
|
//
|
|
ulInt = SPIIntNumberGet(ulBase);
|
|
|
|
//
|
|
// Disable the interrupt.
|
|
//
|
|
IntDisable(ulInt);
|
|
|
|
//
|
|
// Unregister the interrupt handler.
|
|
//
|
|
IntUnregister(ulInt);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables individual SPI interrupt sources.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
|
|
//!
|
|
//! This function enables the indicated SPI interrupt sources. Only the
|
|
//! sources that are enabled can be reflected to the processor interrupt;
|
|
//! disabled sources have no effect on the processor.
|
|
//!
|
|
//! The \e ulIntFlags parameter is the logical OR of any of the following:
|
|
//!
|
|
//! - \b SPI_INT_DMATX
|
|
//! - \b SPI_INT_DMARX
|
|
//! - \b SPI_INT_EOW
|
|
//! - \b SPI_INT_RX_OVRFLOW
|
|
//! - \b SPI_INT_RX_FULL
|
|
//! - \b SPI_INT_TX_UDRFLOW
|
|
//! - \b SPI_INT_TX_EMPTY
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
unsigned long ulDmaMsk;
|
|
|
|
//
|
|
// Enable DMA Tx Interrupt
|
|
//
|
|
if(ulIntFlags & SPI_INT_DMATX)
|
|
{
|
|
ulDmaMsk = SPIDmaMaskGet(ulBase);
|
|
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
|
|
}
|
|
|
|
//
|
|
// Enable DMA Rx Interrupt
|
|
//
|
|
if(ulIntFlags & SPI_INT_DMARX)
|
|
{
|
|
ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1);
|
|
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
|
|
}
|
|
|
|
//
|
|
// Enable the specific Interrupts
|
|
//
|
|
HWREG(ulBase + MCSPI_O_IRQENABLE) |= (ulIntFlags & 0x0003000F);
|
|
}
|
|
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables individual SPI interrupt sources.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
|
|
//!
|
|
//! This function disables the indicated SPI interrupt sources. Only the
|
|
//! sources that are enabled can be reflected to the processor interrupt;
|
|
//! disabled sources have no effect on the processor.
|
|
//!
|
|
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
|
|
//! parameter to SPIIntEnable().
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
unsigned long ulDmaMsk;
|
|
|
|
//
|
|
// Disable DMA Tx Interrupt
|
|
//
|
|
if(ulIntFlags & SPI_INT_DMATX)
|
|
{
|
|
ulDmaMsk = SPIDmaMaskGet(ulBase);
|
|
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
|
|
}
|
|
|
|
//
|
|
// Disable DMA Tx Interrupt
|
|
//
|
|
if(ulIntFlags & SPI_INT_DMARX)
|
|
{
|
|
ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1);
|
|
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
|
|
}
|
|
|
|
//
|
|
// Disable the specific Interrupts
|
|
//
|
|
HWREG(ulBase + MCSPI_O_IRQENABLE) &= ~(ulIntFlags & 0x0003000F);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the current interrupt status.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param bMasked is \b false if the raw interrupt status is required and
|
|
//! \b true if the masked interrupt status is required.
|
|
//!
|
|
//! This function returns the interrupt status for the specified SPI.
|
|
//! The status of interrupts that are allowed to reflect to the processor can
|
|
//! be returned.
|
|
//!
|
|
//! \return Returns the current interrupt status, enumerated as a bit field of
|
|
//! values described in SPIIntEnable().
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
SPIIntStatus(unsigned long ulBase, tBoolean bMasked)
|
|
{
|
|
unsigned long ulIntStat;
|
|
unsigned long ulIntFlag;
|
|
unsigned long ulDmaMsk;
|
|
|
|
//
|
|
// Get SPI interrupt status
|
|
//
|
|
ulIntFlag = HWREG(ulBase + MCSPI_O_IRQSTATUS) & 0x0003000F;
|
|
|
|
if(bMasked)
|
|
{
|
|
ulIntFlag &= HWREG(ulBase + MCSPI_O_IRQENABLE);
|
|
}
|
|
|
|
//
|
|
// Get the interrupt bit
|
|
//
|
|
ulDmaMsk = SPIDmaMaskGet(ulBase);
|
|
|
|
//
|
|
// Get the DMA interrupt status
|
|
//
|
|
if(bMasked)
|
|
{
|
|
ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED);
|
|
}
|
|
else
|
|
{
|
|
ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW);
|
|
}
|
|
|
|
//
|
|
// Get SPI Tx DMA done status
|
|
//
|
|
if(ulIntStat & ulDmaMsk)
|
|
{
|
|
ulIntFlag |= SPI_INT_DMATX;
|
|
}
|
|
|
|
//
|
|
// Get SPI Rx DMA done status
|
|
//
|
|
if(ulIntStat & (ulDmaMsk >> 1))
|
|
{
|
|
ulIntFlag |= SPI_INT_DMARX;
|
|
}
|
|
|
|
//
|
|
// Return status
|
|
//
|
|
return(ulIntFlag);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears SPI interrupt sources.
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
|
|
//!
|
|
//! The specified SPI interrupt sources are cleared, so that they no longer
|
|
//! assert. This function must be called in the interrupt handler to keep the
|
|
//! interrupt from being recognized again immediately upon exit.
|
|
//!
|
|
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
|
|
//! parameter to SPIIntEnable().
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
unsigned long ulDmaMsk;
|
|
|
|
//
|
|
// Disable DMA Tx Interrupt
|
|
//
|
|
if(ulIntFlags & SPI_INT_DMATX)
|
|
{
|
|
ulDmaMsk = SPIDmaMaskGet(ulBase);
|
|
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
|
|
}
|
|
|
|
//
|
|
// Disable DMA Tx Interrupt
|
|
//
|
|
if(ulIntFlags & SPI_INT_DMARX)
|
|
{
|
|
ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1);
|
|
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
|
|
}
|
|
|
|
//
|
|
// Clear Interrupts
|
|
//
|
|
HWREG(ulBase + MCSPI_O_IRQSTATUS) = (ulIntFlags & 0x0003000F);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables the chip select in software controlled mode
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module.
|
|
//!
|
|
//! This function enables the Chip select in software controlled mode. The
|
|
//! active state of CS will depend on the configuration done via
|
|
//! \sa SPIConfigExpClkSet().
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void SPICSEnable(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Set Chip Select enable bit.
|
|
//
|
|
HWREG( ulBase+MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables the chip select in software controlled mode
|
|
//!
|
|
//! \param ulBase is the base address of the SPI module.
|
|
//!
|
|
//! This function disables the Chip select in software controlled mode. The
|
|
//! active state of CS will depend on the configuration done via
|
|
//! sa SPIConfigSetExpClk().
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void SPICSDisable(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Reset Chip Select enable bit.
|
|
//
|
|
HWREG( ulBase+MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Send/Receive data buffer over SPI channel
|
|
//!
|
|
//! \param ulBase is the base address of SPI module
|
|
//! \param ucDout is the pointer to Tx data buffer or 0.
|
|
//! \param ucDin is pointer to Rx data buffer or 0
|
|
//! \param ulCount is the size of data in bytes.
|
|
//! \param ulFlags controlls chip select toggling.
|
|
//!
|
|
//! This function transfers \e ulCount bytes of data over SPI channel. Since
|
|
//! the API sends a SPI word at a time \e ulCount should be a multiple of
|
|
//! word length set using SPIConfigSetExpClk().
|
|
//!
|
|
//! If the \e ucDout parameter is set to 0, the function will send 0xFF over
|
|
//! the SPI MOSI line.
|
|
//!
|
|
//! If the \e ucDin parameter is set to 0, the function will ignore data on SPI
|
|
//! MISO line.
|
|
//!
|
|
//! The parameter \e ulFlags is logical OR of one or more of the following
|
|
//!
|
|
//! - \b SPI_CS_ENABLE if CS needs to be enabled at start of transfer.
|
|
//! - \b SPI_CS_DISABLE if CS need to be disabled at the end of transfer.
|
|
//!
|
|
//! This function will not return until data has been transmitted
|
|
//!
|
|
//! \return Returns 0 on success, -1 otherwise.
|
|
//
|
|
//*****************************************************************************
|
|
long SPITransfer(unsigned long ulBase, unsigned char *ucDout,
|
|
unsigned char *ucDin, unsigned long ulCount,
|
|
unsigned long ulFlags)
|
|
{
|
|
unsigned long ulWordLength;
|
|
long lRet;
|
|
|
|
//
|
|
// Get the word length
|
|
//
|
|
ulWordLength = (HWREG(ulBase + MCSPI_O_CH0CONF) & MCSPI_CH0CONF_WL_M);
|
|
|
|
//
|
|
// Check for word length.
|
|
//
|
|
if( !((ulWordLength == SPI_WL_8) || (ulWordLength == SPI_WL_16) ||
|
|
(ulWordLength == SPI_WL_32)) )
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
if( ulWordLength == SPI_WL_8 )
|
|
{
|
|
//
|
|
// Do byte transfer
|
|
//
|
|
lRet = SPITransfer8(ulBase,ucDout,ucDin,ulCount,ulFlags);
|
|
}
|
|
else if( ulWordLength == SPI_WL_16 )
|
|
{
|
|
|
|
//
|
|
// Do half-word transfer
|
|
//
|
|
lRet = SPITransfer16(ulBase,(unsigned short *)ucDout,
|
|
(unsigned short *)ucDin,ulCount,ulFlags);
|
|
}
|
|
else
|
|
{
|
|
//
|
|
// Do word transfer
|
|
//
|
|
lRet = SPITransfer32(ulBase,(unsigned long *)ucDout,
|
|
(unsigned long *)ucDin,ulCount,ulFlags);
|
|
}
|
|
|
|
//
|
|
// return
|
|
//
|
|
return lRet;
|
|
|
|
}
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|