kopia lustrzana https://github.com/micropython/micropython
112 wiersze
3.4 KiB
C
112 wiersze
3.4 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2024 Arduino SA
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* libmetal mimxrt port.
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*/
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "fsl_common.h"
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#include "fsl_mu.h"
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#include CPU_HEADER_H
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#include "metal/sys.h"
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#include "metal/utilities.h"
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#include "metal/device.h"
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struct metal_state _metal;
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static mp_sched_node_t rproc_notify_node;
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#define IRQ_PRI_MU NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 10, 0)
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int metal_sys_init(const struct metal_init_params *params) {
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metal_unused(params);
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// Init MU.
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MU_Init(MUA);
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// Configure and enable MU IRQs.
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MU_ClearStatusFlags(MUA, kMU_GenInt0Flag);
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NVIC_SetPriority(MUA_IRQn, IRQ_PRI_MU);
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NVIC_EnableIRQ(MUA_IRQn);
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MU_EnableInterrupts(MUA, kMU_GenInt0InterruptEnable);
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#ifndef VIRTIO_USE_DCACHE
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// If cache management is not enabled, configure the MPU to disable caching
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// for the entire shared memory region.
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ARM_MPU_Disable();
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MPU->RBAR = ARM_MPU_RBAR(10, METAL_MPU_REGION_BASE);
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// Normal type, not shareable, non-cacheable
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, METAL_MPU_REGION_SIZE);
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
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#endif
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metal_bus_register(&metal_generic_bus);
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return 0;
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}
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void metal_sys_finish(void) {
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NVIC_DisableIRQ(MUA_IRQn);
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metal_bus_unregister(&metal_generic_bus);
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}
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unsigned int sys_irq_save_disable(void) {
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return disable_irq();
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}
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void sys_irq_restore_enable(unsigned int state) {
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enable_irq(state);
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}
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void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
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size_t size, unsigned int flags) {
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metal_unused(pa);
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metal_unused(size);
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metal_unused(flags);
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return va;
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}
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void metal_machine_cache_flush(void *addr, unsigned int len) {
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SCB_CleanDCache_by_Addr(addr, len);
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}
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void metal_machine_cache_invalidate(void *addr, unsigned int len) {
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SCB_InvalidateDCache_by_Addr(addr, len);
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}
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int metal_rproc_notify(void *priv, uint32_t id) {
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MU_TriggerInterrupts(MUA, kMU_GenInt0InterruptTrigger);
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return 0;
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}
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void MUA_IRQHandler(void) {
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if (MU_GetStatusFlags(MUA) & kMU_GenInt0Flag) {
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MU_ClearStatusFlags(MUA, kMU_GenInt0Flag);
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mp_sched_schedule_node(&rproc_notify_node, openamp_remoteproc_notified);
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}
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__DSB();
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}
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