This updates ESP IDF to use v3.3-beta3. And also adjusts README.md to
point to stable docs which provide a link to download the correct toolchain
for this IDF version, namely 1.22.0-80-g6c4433a-5.2.0
Previously the end of the heap was the start (lowest address) of the stack.
With the changes in this commit these addresses are now independent,
allowing a board to place the heap and stack in separate locations.
With this the user can select multiple logical units to expose over USB MSC
at once, eg: pyb.usb_mode('VCP+MSC', msc=(pyb.Flash(), pyb.SDCard())). The
default behaviour is the original behaviour of just one unit at a time.
Eventually these responses could be filled in by a function to make their
contents dynamic, depending on the attached logical units. But for now
they are fixed, and this patch fixes the MODE SENSE(6) responses so it is
the correct length with the correct header.
SCSI can support multiple logical units over the one interface (in this
case over USBD MSC) and here the MSC code is reworked to support this
feature. At this point only one LU is used and the behaviour is mostly
unchanged from before, except the INQUIRY result is different (it will
report "Flash" for both flash and SD card).
To use it a board should define MICROPY_PY_USSL=1 and MICROPY_SSL_MBEDTLS=1
at the Makefile level. With the provided configuration it adds about 64k
to the build.
It doesn't work to tie the polling of an underlying NIC driver (eg to check
the NIC for pending Ethernet frames) with its associated lwIP netif. This
is because most NICs are implemented with IRQs and don't need polling,
because there can be multiple lwIP netif's per NIC driver, and because it
restricts the use of the netif->state variable. Instead the NIC should
have its own specific way of processing incoming Ethernet frame.
This patch removes this generic NIC polling feature, and for the only
driver that uses it (Wiznet5k) replaces it with an explicit call to the
poll function (which could eventually be improved by using a proper
external interrupt).
This adds support for SD cards using the ESP32's built-in hardware SD/MMC
host controller, over either the SDIO bus or SPI. The class is available
as machine.SDCard and using it can be as simple as:
uos.mount(machine.SDCard(), '/sd')
If the board-pin name is left empty then only the cpu-pin name is used, eg
",PA0". If the board-pin name starts with a hyphen then it's available as
a C definition but not in the firmware, eg "-X1,PA0".
The patch solves the problem where multiple Timer objects (e.g. multiple
Timer(0) instances) could initialise multiple handles to the same internal
timer. The list of timers is now maintained not for "active" timers (where
init is called), but for all timers created. The timers are only removed
from the list of timers on soft-reset (machine_timer_deinit_all).
Fixes#4078.
The board config option MICROPY_HW_USB_ENABLE_CDC2 is now changed to
MICROPY_HW_USB_CDC_NUM, and the latter should be defined to the maximum
number of CDC interfaces to support (defaults to 1).
Set the active MPU region to the actual size of SDRAM configured and
invalidate the rest of the memory-mapped region, to prevent errors due to
CPU speculation. Also update the attributes of the SDRAM region as per ST
recommendations, and change region numbers to avoid conflicts elsewhere in
the codebase (see eth usage).
I2C can't be enabled in prj_base.conf because it's a board-specific
feature. For example, if a board doesn't have I2C but CONFIG_I2C=y then
the build will fail (on Zephyr build system side). The patch here gets the
qemu_cortex_m3 build working again.
This enables going back to previous wrapped lines using backspace or left
arrow: instead of just sticking to the beginning of a line, the cursor will
move a line up.
On MCUs that have an I2C TIMINGR register, this can now be explicitly set
via the "timingr" keyword argument to the I2C constructor, for both
machine.I2C and pyb.I2C. This allows to configure precise timing values
when the defaults are inadequate.
Previously the hardware I2C timeout was hard coded to 50ms which isn't
guaranteed to be enough depending on the clock stretching specs of the I2C
device(s) in use.
This patch ensures the hardware I2C implementation honors the existing
timeout argument passed to the machine.I2C constructor. The default
timeout for software and hardware I2C is now 50ms.
Damien George