Wykres commitów

7 Commity (master)

Autor SHA1 Wiadomość Data
Angus Gratton 8b1980ad45 samd: Use unique id for USB serial number.
Replaces the previous all-zeroes "TODO" serial number.

Requires refactoring the low-level unique_id routine out from modmachine.c.

This work was funded through GitHub Sponsors.

Signed-off-by: Angus Gratton <angus@redyak.com.au>
2023-11-16 15:03:09 +11:00
Angus Gratton 26d5032980 samd: Switch TinyUSB to run via a scheduled task.
Previously the TinyUSB task was run in the ISR immediately after the
interrupt handler.  This approach gives very similar performance (no change
in CDC throughput tests) but reduces the amount of time spent in the ISR,
and allows TinyUSB callbacks to run in thread mode.

This work was funded through GitHub Sponsors.

Signed-off-by: Angus Gratton <angus@redyak.com.au>
2023-11-09 12:30:04 +11:00
Damien George 5b4a2baff6 extmod/machine_uart: Factor ports' UART Python bindings to common code.
This is a code factoring to have the Python bindings in one location, and
all the ports use those same bindings.  For all ports except the two listed
below there is no functional change.

The nrf port has UART.sendbreak() removed, but this method previously did
nothing.

The zephyr port has the following methods added:
- UART.init(): supports setting timeout and timeout_char.
- UART.deinit(): does nothing, just returns None.
- UART.flush(): raises OSError(EINVAL) because it's not implemented.
- UART.any() and UART.txdone(): raise NotImplementedError.

Signed-off-by: Damien George <damien@micropython.org>
2023-10-26 10:46:42 +11:00
robert-hh 3625388d8c samd/samd_isr: Change the way a Sercom ISR is registered and called.
Code size diff: +12 Bytes
BSS diff: -12 Bytes
RAM usage: +16 Bytes
Speed increase: a few clock cycles per call
Style improvement: ++
2022-10-06 22:52:10 +11:00
robert-hh b4d29fd47a samd/clock_config: Set up the clock configuration.
Clock settings:
- GCLK0: 48 MHz (SAMD21) or 120 MHz(SAMD51).
- GCLK1: 32768 Hz for driving the PLL.
- GCLK2: 48 MHz for tzhe peripheral clock.
- GCLK3: 1 MHz (SAMD21) or 8 MHz (SAMD51) for the µs ticks timer.
- GCLK8: 1 kHz for WDT (SAMD21 only).

If a 32 kHz crystal is present, it will be used as clock source.  Otherwise
the DFLL48M in open-loop mode is used.

GCLK0 for SAM51 can be changed between 48 MHz and 200 MHz.  The specified
range is 96 MHz - 120 MHz.
2022-10-06 22:33:31 +11:00
Peter van der Burg 4c132614e1 samd/samd_soc: Allow a board to configure the low-level MCU config.
The board specific #defines will be moved to individual boards.
2021-11-19 11:42:47 +11:00
Damien George 5f9bd11527 samd: Add new port to Microchip SAMDxx microcontrollers.
Initially supporting SAMD21 and SAMD51.
2019-07-01 17:19:18 +10:00