For all MCUs: run the test for USB clock recovery mode fallback after USB
has been started.
For samd21: change DFLL48 config from the open loop mode variant to sync
with the XOSC32KULP. Matches better the 48MHz value.
Signed-off-by: robert-hh <robert@hammelrath.com>
Two new compile flags are:
MICROPY_HW_DFLL_USB_SYNC: Effective only if DFLL48 does not run from the
crystal. It will synchronize the DFLL48M clock with the USB's SOF pulse.
If no USB is connected, it will fall back to open loop mode. The DFLL48M
clock is then pretty precise, but with a higher clock jitter at SAMD51
devices.
MICROPY_HW_MCU_OSC32KULP: Effective only if the devics uses a crystal as
clock source. Run the MCU clock from the ULP 32kHz oszillator instead of
the crystal. This flag was added to cater for a interference problem of
the crystal and Neopixel/Debug pins at Adafruit FEATHER Mx boards, which
causes the board to crash. Drawback: ticks_ms() and time.time() vs. than
ticks_us() and the peripherals like PWM run at not synchronous clocks.
Clock settings:
- GCLK0: 48 MHz (SAMD21) or 120 MHz(SAMD51).
- GCLK1: 32768 Hz for driving the PLL.
- GCLK2: 48 MHz for tzhe peripheral clock.
- GCLK3: 1 MHz (SAMD21) or 8 MHz (SAMD51) for the µs ticks timer.
- GCLK8: 1 kHz for WDT (SAMD21 only).
If a 32 kHz crystal is present, it will be used as clock source. Otherwise
the DFLL48M in open-loop mode is used.
GCLK0 for SAM51 can be changed between 48 MHz and 200 MHz. The specified
range is 96 MHz - 120 MHz.
robert-hh