From fd10a11c6bbed4c237e6f099b0161352b7913fa5 Mon Sep 17 00:00:00 2001 From: Damien George Date: Fri, 17 Aug 2018 01:11:06 +1000 Subject: [PATCH] py/asmxtensa: Fix bug with order of regs in addi encoding. --- py/asmxtensa.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/py/asmxtensa.h b/py/asmxtensa.h index 5198e0199e..9a8ef45c0c 100644 --- a/py/asmxtensa.h +++ b/py/asmxtensa.h @@ -118,7 +118,7 @@ static inline void asm_xtensa_op_add(asm_xtensa_t *as, uint reg_dest, uint reg_s } static inline void asm_xtensa_op_addi(asm_xtensa_t *as, uint reg_dest, uint reg_src, int imm8) { - asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 12, reg_dest, reg_src, imm8 & 0xff)); + asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 12, reg_src, reg_dest, imm8 & 0xff)); } static inline void asm_xtensa_op_and(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {