From c568a2b44387bee14ea5f427a6e9b736eb1b5345 Mon Sep 17 00:00:00 2001 From: Damien George Date: Sat, 4 Oct 2014 01:54:02 +0100 Subject: [PATCH] stmhal: Adjust computation of SYSCLK to retain precision. --- stmhal/hal/src/stm32f4xx_hal_rcc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/stmhal/hal/src/stm32f4xx_hal_rcc.c b/stmhal/hal/src/stm32f4xx_hal_rcc.c index bda08db3f0..dbebbf182a 100644 --- a/stmhal/hal/src/stm32f4xx_hal_rcc.c +++ b/stmhal/hal/src/stm32f4xx_hal_rcc.c @@ -972,7 +972,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if (__RCC_PLLSRC() != 0) { /* HSE used as PLL clock source */ - pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + // dpgeorge: Adjust the way the arithmetic is done so it retains + // precision for the case that pllm doesn't evenly divide HSE_VALUE. + // Must be sure not to overflow, so divide by 4 first. HSE_VALUE + // should be a multiple of 4 (being a multiple of 100 is enough). + pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4; } else {