kopia lustrzana https://github.com/micropython/micropython
stm32/i2c: Add new hardware I2C driver for F4 MCUs.
This driver uses low-level register access to control the I2C peripheral (ie it doesn't rely on the ST HAL) and provides the same C-level API as the existing F7 hardware driver.pull/3784/head
Damien George
rodzic
ca36645410
commit
b21415ed4f
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@ -30,10 +30,240 @@
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#if MICROPY_HW_ENABLE_HW_I2C
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#if defined(STM32F7)
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#define I2C_POLL_TIMEOUT_MS (50)
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#if defined(STM32F4)
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int i2c_init(i2c_t *i2c, mp_hal_pin_obj_t scl, mp_hal_pin_obj_t sda, uint32_t freq) {
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uint32_t i2c_id = ((uint32_t)i2c - I2C1_BASE) / (I2C2_BASE - I2C1_BASE);
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// Init pins
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if (!mp_hal_pin_config_alt(scl, MP_HAL_PIN_MODE_ALT_OPEN_DRAIN, MP_HAL_PIN_PULL_UP, AF_FN_I2C, i2c_id + 1)) {
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return -MP_EPERM;
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}
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if (!mp_hal_pin_config_alt(sda, MP_HAL_PIN_MODE_ALT_OPEN_DRAIN, MP_HAL_PIN_PULL_UP, AF_FN_I2C, i2c_id + 1)) {
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return -MP_EPERM;
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}
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// Force reset I2C peripheral
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RCC->APB1RSTR |= RCC_APB1RSTR_I2C1RST << i2c_id;
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RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST << i2c_id);
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// Enable I2C peripheral clock
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN << i2c_id;
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volatile uint32_t tmp = RCC->APB1ENR; // delay after RCC clock enable
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(void)tmp;
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uint32_t PCLK1 = HAL_RCC_GetPCLK1Freq();
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// Initialise I2C peripheral
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i2c->CR1 = 0;
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i2c->CR2 = PCLK1 / 1000000;
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i2c->OAR1 = 0;
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i2c->OAR2 = 0;
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freq = MIN(freq, 400000);
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// SM: MAX(4, PCLK1 / (F * 2))
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// FM, 16:9 duty: 0xc000 | MAX(1, (PCLK1 / (F * (16 + 9))))
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if (freq <= 100000) {
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i2c->CCR = MAX(4, PCLK1 / (freq * 2));
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} else {
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i2c->CCR = 0xc000 | MAX(1, PCLK1 / (freq * 25));
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}
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// SM: 1000ns / (1/PCLK1) + 1 = PCLK1 * 1e-6 + 1
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// FM: 300ns / (1/PCLK1) + 1 = 300e-3 * PCLK1 * 1e-6 + 1
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if (freq <= 100000) {
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i2c->TRISE = PCLK1 / 1000000 + 1; // 1000ns rise time in SM
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} else {
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i2c->TRISE = PCLK1 / 1000000 * 3 / 10 + 1; // 300ns rise time in FM
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}
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#if defined(I2C_FLTR_ANOFF)
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i2c->FLTR = 0; // analog filter on, digital filter off
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#endif
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return 0;
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}
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STATIC int i2c_wait_sr1_set(i2c_t *i2c, uint32_t mask) {
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uint32_t t0 = HAL_GetTick();
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while (!(i2c->SR1 & mask)) {
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if (HAL_GetTick() - t0 >= I2C_POLL_TIMEOUT_MS) {
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i2c->CR1 &= ~I2C_CR1_PE;
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return -MP_ETIMEDOUT;
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}
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}
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return 0;
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}
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STATIC int i2c_wait_stop(i2c_t *i2c) {
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uint32_t t0 = HAL_GetTick();
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while (i2c->CR1 & I2C_CR1_STOP) {
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if (HAL_GetTick() - t0 >= I2C_POLL_TIMEOUT_MS) {
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i2c->CR1 &= ~I2C_CR1_PE;
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return -MP_ETIMEDOUT;
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}
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}
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i2c->CR1 &= ~I2C_CR1_PE;
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return 0;
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}
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// For write: len = 0, 1 or N
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// For read: len = 1, 2 or N; stop = true
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int i2c_start_addr(i2c_t *i2c, int rd_wrn, uint16_t addr, size_t next_len, bool stop) {
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if (!(i2c->CR1 & I2C_CR1_PE) && (i2c->SR2 & I2C_SR2_MSL)) {
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// The F4 I2C peripheral can sometimes get into a bad state where it's disabled
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// (PE low) but still an active master (MSL high). It seems the best way to get
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// out of this is a full reset.
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uint32_t i2c_id = ((uint32_t)i2c - I2C1_BASE) / (I2C2_BASE - I2C1_BASE);
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RCC->APB1RSTR |= RCC_APB1RSTR_I2C1RST << i2c_id;
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RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST << i2c_id);
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}
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// It looks like it's possible to terminate the reading by sending a
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// START condition instead of STOP condition but we don't support that.
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if (rd_wrn) {
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if (!stop) {
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return -MP_EINVAL;
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}
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}
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// Repurpose OAR1 to hold stop flag
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i2c->OAR1 = stop;
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// Enable peripheral and send START condition
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i2c->CR1 |= I2C_CR1_PE;
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i2c->CR1 |= I2C_CR1_START;
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// Wait for START to be sent
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int ret;
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if ((ret = i2c_wait_sr1_set(i2c, I2C_SR1_SB))) {
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return ret;
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}
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// Send the 7-bit address with read/write bit
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i2c->DR = addr << 1 | rd_wrn;
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// Wait for address to be sent
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if ((ret = i2c_wait_sr1_set(i2c, I2C_SR1_AF | I2C_SR1_ADDR))) {
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return ret;
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}
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// Check if the slave responded or not
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if (i2c->SR1 & I2C_SR1_AF) {
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// Got a NACK
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i2c->CR1 |= I2C_CR1_STOP;
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i2c_wait_stop(i2c); // Don't leak errors from this call
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return -MP_ENODEV;
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}
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if (rd_wrn) {
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// For reading, set up ACK/NACK control based on number of bytes to read (at least 1 byte)
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if (next_len <= 1) {
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// NACK next received byte
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i2c->CR1 &= ~I2C_CR1_ACK;
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} else if (next_len <= 2) {
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// NACK second received byte
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i2c->CR1 |= I2C_CR1_POS;
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i2c->CR1 &= ~I2C_CR1_ACK;
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} else {
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// ACK next received byte
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i2c->CR1 |= I2C_CR1_ACK;
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}
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}
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// Read SR2 to clear SR1_ADDR
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uint32_t sr2 = i2c->SR2;
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(void)sr2;
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return 0;
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}
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// next_len = 0 or N (>=2)
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int i2c_read(i2c_t *i2c, uint8_t *dest, size_t len, size_t next_len) {
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if (len == 0) {
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return -MP_EINVAL;
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}
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if (next_len == 1) {
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return -MP_EINVAL;
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}
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size_t remain = len + next_len;
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if (remain == 1) {
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// Special case
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i2c->CR1 |= I2C_CR1_STOP;
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int ret;
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if ((ret = i2c_wait_sr1_set(i2c, I2C_SR1_RXNE))) {
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return ret;
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}
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*dest = i2c->DR;
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} else {
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for (; len; --len) {
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remain = len + next_len;
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int ret;
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if ((ret = i2c_wait_sr1_set(i2c, I2C_SR1_BTF))) {
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return ret;
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}
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if (remain == 2) {
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// In this case next_len == 0 (it's not allowed to be 1)
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i2c->CR1 |= I2C_CR1_STOP;
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*dest++ = i2c->DR;
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*dest = i2c->DR;
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break;
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} else if (remain == 3) {
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// NACK next received byte
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i2c->CR1 &= ~I2C_CR1_ACK;
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}
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*dest++ = i2c->DR;
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}
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}
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if (!next_len) {
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// We sent a stop above, just wait for it to be finished
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return i2c_wait_stop(i2c);
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}
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return 0;
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}
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// next_len = 0 or N
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int i2c_write(i2c_t *i2c, const uint8_t *src, size_t len, size_t next_len) {
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int ret;
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if ((ret = i2c_wait_sr1_set(i2c, I2C_SR1_AF | I2C_SR1_TXE))) {
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return ret;
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}
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// Write out the data
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int num_acks = 0;
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while (len--) {
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i2c->DR = *src++;
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if ((ret = i2c_wait_sr1_set(i2c, I2C_SR1_AF | I2C_SR1_BTF))) {
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return ret;
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}
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if (i2c->SR1 & I2C_SR1_AF) {
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// Slave did not respond to byte so stop sending
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break;
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}
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++num_acks;
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}
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if (!next_len) {
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if (i2c->OAR1) {
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// Send a STOP and wait for it to finish
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i2c->CR1 |= I2C_CR1_STOP;
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if ((ret = i2c_wait_stop(i2c))) {
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return ret;
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}
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}
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}
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return num_acks;
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}
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#elif defined(STM32F7)
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int i2c_init(i2c_t *i2c, mp_hal_pin_obj_t scl, mp_hal_pin_obj_t sda, uint32_t freq) {
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uint32_t i2c_id = ((uint32_t)i2c - I2C1_BASE) / (I2C2_BASE - I2C1_BASE);
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@ -214,6 +444,10 @@ int i2c_write(i2c_t *i2c, const uint8_t *src, size_t len, size_t next_len) {
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return num_acks;
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}
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#endif
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#if defined(STM32F4) || defined(STM32F7)
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int i2c_readfrom(i2c_t *i2c, uint16_t addr, uint8_t *dest, size_t len, bool stop) {
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int ret;
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if ((ret = i2c_start_addr(i2c, 1, addr, len, stop))) {
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@ -230,6 +464,6 @@ int i2c_writeto(i2c_t *i2c, uint16_t addr, const uint8_t *src, size_t len, bool
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return i2c_write(i2c, src, len, 0);
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}
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#endif // defined(STM32F7)
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#endif
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#endif // MICROPY_HW_ENABLE_HW_I2C
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