kopia lustrzana https://github.com/micropython/micropython
stm32/timer: Make timer_get_source_freq more efficient by using regs.
Use direct register access to get the APB clock divider. This reduces code size and makes the code more efficient.pull/3750/merge
rodzic
070937fe93
commit
5c0685912f
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@ -228,25 +228,27 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
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// APB clock. Otherwise (APB prescaler > 1) the timer clock is twice its
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// APB clock. Otherwise (APB prescaler > 1) the timer clock is twice its
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// respective APB clock. See DM00031020 Rev 4, page 115.
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// respective APB clock. See DM00031020 Rev 4, page 115.
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uint32_t timer_get_source_freq(uint32_t tim_id) {
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uint32_t timer_get_source_freq(uint32_t tim_id) {
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uint32_t source;
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uint32_t source, clk_div;
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uint32_t latency;
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RCC_ClkInitTypeDef rcc_init;
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// Get clock config.
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HAL_RCC_GetClockConfig(&rcc_init, &latency);
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if (tim_id == 1 || (8 <= tim_id && tim_id <= 11)) {
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if (tim_id == 1 || (8 <= tim_id && tim_id <= 11)) {
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// TIM{1,8,9,10,11} are on APB2
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// TIM{1,8,9,10,11} are on APB2
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source = HAL_RCC_GetPCLK2Freq();
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source = HAL_RCC_GetPCLK2Freq();
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if (rcc_init.APB2CLKDivider != RCC_HCLK_DIV1) {
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#if defined(STM32H7)
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source *= 2;
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clk_div = RCC->D2CFGR & RCC_D2CFGR_D2PPRE2;
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}
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#else
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clk_div = RCC->CFGR & RCC_CFGR_PPRE2;
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#endif
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} else {
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} else {
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// TIM{2,3,4,5,6,7,12,13,14} are on APB1
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// TIM{2,3,4,5,6,7,12,13,14} are on APB1
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source = HAL_RCC_GetPCLK1Freq();
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source = HAL_RCC_GetPCLK1Freq();
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if (rcc_init.APB1CLKDivider != RCC_HCLK_DIV1) {
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#if defined(STM32H7)
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source *= 2;
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clk_div = RCC->D2CFGR & RCC_D2CFGR_D2PPRE1;
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#else
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clk_div = RCC->CFGR & RCC_CFGR_PPRE1;
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#endif
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}
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}
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if (clk_div != 0) {
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// APB prescaler for this timer is > 1
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source *= 2;
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}
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}
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return source;
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return source;
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}
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}
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