kopia lustrzana https://github.com/micropython/micropython
ports: mimxrt: Switch to official GitHub SDK.
The current nxp_sdk is being replaced with official mcux-sdk in upstream repository(originally used in tinyUSB). Switching to the mcux-sdk only affects mimxrt ports for now however this will make porting other families easier. Signed-off-by: Yilin Sun <imi415@imi.moe>pull/11516/head
Yilin Sun
rodzic
5114f2c1ea
commit
55d855dc67
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@ -33,9 +33,6 @@
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[submodule "lib/btstack"]
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path = lib/btstack
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url = https://github.com/bluekitchen/btstack.git
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[submodule "lib/nxp_driver"]
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path = lib/nxp_driver
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url = https://github.com/hathach/nxp_driver.git
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[submodule "lib/libhydrogen"]
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path = lib/libhydrogen
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url = https://github.com/jedisct1/libhydrogen.git
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@ -68,3 +65,6 @@
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[submodule "lib/arduino-lib"]
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path = lib/arduino-lib
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url = https://github.com/arduino/arduino-lib-mpy.git
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[submodule "lib/mcux-sdk"]
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path = lib/mcux-sdk
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url = https://github.com/nxp-mcuxpresso/mcux-sdk.git
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@ -0,0 +1 @@
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Subproject commit 59b549a30b23cd1b3727a0ae83e7f94404d736af
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@ -1 +0,0 @@
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Subproject commit fa5a554c7944d2a196626f8d3631e44943f9abcc
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@ -20,7 +20,7 @@ endif
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BUILD ?= build-$(BOARD)
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PORT ?= /dev/ttyACM0
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CROSS_COMPILE ?= arm-none-eabi-
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GIT_SUBMODULES += lib/tinyusb lib/nxp_driver
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GIT_SUBMODULES += lib/tinyusb lib/mcux-sdk
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# MicroPython feature configurations
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MICROPY_VFS_LFS2 ?= 1
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@ -51,7 +51,8 @@ include $(TOP)/py/py.mk
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include $(TOP)/extmod/extmod.mk
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# Set SDK directory based on MCU_SERIES
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MCU_DIR = lib/nxp_driver/sdk/devices/$(MCU_SERIES)
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MCUX_SDK_DIR = lib/mcux-sdk
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MCU_DIR = $(MCUX_SDK_DIR)/devices/$(MCU_SERIES)
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# Select linker scripts based on MCU_SERIES
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LD_FILES = boards/$(MCU_SERIES).ld boards/common.ld
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@ -71,8 +72,6 @@ GEN_PINS_SRC = $(BUILD)/pins_gen.c
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INC += -I$(BOARD_DIR)
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INC += -I$(BUILD)
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INC += -I$(TOP)
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INC += -I$(TOP)/$(MCU_DIR)
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INC += -I$(TOP)/$(MCU_DIR)/drivers
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INC += -I$(TOP)/lib/cmsis/inc
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INC += -I$(TOP)/lib/oofatfs
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INC += -I$(TOP)/lib/tinyusb/hw
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@ -109,36 +108,39 @@ SRC_TINYUSB_C += \
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# All settings for Ethernet support are controller by the value of MICROPY_PY_LWIP
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ifeq ($(MICROPY_PY_LWIP),1)
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SRC_ETH_C += \
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$(MCU_DIR)/drivers/fsl_enet.c \
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$(MCUX_SDK_DIR)/drivers/enet/fsl_enet.c \
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hal/phy/device/phydp83825/fsl_phydp83825.c \
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hal/phy/device/phydp83848/fsl_phydp83848.c \
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hal/phy/device/phyksz8081/fsl_phyksz8081.c \
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hal/phy/device/phylan8720/fsl_phylan8720.c \
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hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.c \
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hal/phy/mdio/enet/fsl_enet_mdio.c
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INC_HAL_IMX += \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/enet
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endif
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# NXP SDK sources
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SRC_HAL_IMX_C += \
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$(MCU_DIR)/drivers/fsl_clock.c \
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$(MCU_DIR)/drivers/fsl_common.c \
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$(MCU_DIR)/drivers/fsl_dmamux.c \
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$(MCU_DIR)/drivers/fsl_edma.c \
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$(MCU_DIR)/drivers/fsl_flexram.c \
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$(MCU_DIR)/drivers/fsl_flexspi.c \
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$(MCU_DIR)/drivers/fsl_gpc.c \
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$(MCU_DIR)/drivers/fsl_gpio.c \
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$(MCU_DIR)/drivers/fsl_gpt.c \
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$(MCU_DIR)/drivers/fsl_lpi2c.c \
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$(MCU_DIR)/drivers/fsl_lpspi.c \
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$(MCU_DIR)/drivers/fsl_lpspi_edma.c \
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$(MCU_DIR)/drivers/fsl_lpuart.c \
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$(MCU_DIR)/drivers/fsl_pit.c \
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$(MCU_DIR)/drivers/fsl_pwm.c \
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$(MCU_DIR)/drivers/fsl_sai.c \
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$(MCU_DIR)/drivers/fsl_snvs_hp.c \
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$(MCU_DIR)/drivers/fsl_snvs_lp.c \
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$(MCU_DIR)/drivers/fsl_wdog.c \
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$(MCUX_SDK_DIR)/drivers/common/fsl_common.c \
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$(MCUX_SDK_DIR)/drivers/common/fsl_common_arm.c \
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$(MCUX_SDK_DIR)/drivers/dmamux/fsl_dmamux.c \
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$(MCUX_SDK_DIR)/drivers/edma/fsl_edma.c \
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$(MCUX_SDK_DIR)/drivers/flexram/fsl_flexram.c \
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$(MCUX_SDK_DIR)/drivers/flexspi/fsl_flexspi.c \
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$(MCUX_SDK_DIR)/drivers/igpio/fsl_gpio.c \
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$(MCUX_SDK_DIR)/drivers/gpt/fsl_gpt.c \
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$(MCUX_SDK_DIR)/drivers/lpi2c/fsl_lpi2c.c \
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$(MCUX_SDK_DIR)/drivers/lpspi/fsl_lpspi.c \
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$(MCUX_SDK_DIR)/drivers/lpspi/fsl_lpspi_edma.c \
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$(MCUX_SDK_DIR)/drivers/lpuart/fsl_lpuart.c \
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$(MCUX_SDK_DIR)/drivers/pit/fsl_pit.c \
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$(MCUX_SDK_DIR)/drivers/pwm/fsl_pwm.c \
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$(MCUX_SDK_DIR)/drivers/sai/fsl_sai.c \
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$(MCUX_SDK_DIR)/drivers/snvs_hp/fsl_snvs_hp.c \
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$(MCUX_SDK_DIR)/drivers/snvs_lp/fsl_snvs_lp.c \
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$(MCUX_SDK_DIR)/drivers/wdog01/fsl_wdog.c \
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$(MCU_DIR)/system_$(MCU_SERIES)$(MCU_CORE).c \
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# Use a specific boot header for 1062 so the Teensy loader doesn't erase the filesystem.
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@ -148,39 +150,81 @@ else
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SRC_HAL_IMX_C += $(MCU_DIR)/xip/fsl_flexspi_nor_boot.c
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endif
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INC_HAL_IMX += \
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-I$(TOP)/$(MCU_DIR) \
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-I$(TOP)/$(MCU_DIR)/drivers \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/common \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/dmamux \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/edma \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/flexram \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/flexspi \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/igpio \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/gpt \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/lpi2c \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/lpspi \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/lpuart \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/pit \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/pwm \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/sai \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/snvs_hp \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/snvs_lp \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/wdog01 \
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ifeq ($(MICROPY_HW_SDRAM_AVAIL),1)
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SRC_HAL_IMX_C += $(MCU_DIR)/drivers/fsl_semc.c
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SRC_HAL_IMX_C += $(MCUX_SDK_DIR)/drivers/semc/fsl_semc.c
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INC_HAL_IMX += -I$(TOP)/$(MCUX_SDK_DIR)/drivers/semc
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endif
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ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES), MIMXRT1021 MIMXRT1052 MIMXRT1062 MIMXRT1064 MIMXRT1176))
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SRC_HAL_IMX_C += $(MCU_DIR)/drivers/fsl_usdhc.c
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SRC_HAL_IMX_C += $(MCUX_SDK_DIR)/drivers/usdhc/fsl_usdhc.c
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INC_HAL_IMX += -I$(TOP)/$(MCUX_SDK_DIR)/drivers/usdhc
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endif
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ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES), MIMXRT1015 MIMXRT1021 MIMXRT1052 MIMXRT1062 MIMXRT1064 MIMXRT1176))
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SRC_HAL_IMX_C += \
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$(MCU_DIR)/drivers/fsl_qtmr.c \
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$(MCUX_SDK_DIR)/drivers/qtmr_1/fsl_qtmr.c \
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$(MCU_DIR)/drivers/fsl_romapi.c
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INC_HAL_IMX += -I$(TOP)/$(MCUX_SDK_DIR)/drivers/qtmr_1
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endif
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ifeq ($(MCU_SERIES), MIMXRT1176)
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INC += -I$(TOP)/$(MCU_DIR)/drivers/cm7
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SRC_HAL_IMX_C += \
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$(MCU_DIR)/drivers/cm7/fsl_cache.c \
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$(MCU_DIR)/drivers/fsl_dcdc.c \
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$(MCU_DIR)/drivers/fsl_pmu.c \
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$(MCU_DIR)/drivers/fsl_common_arm.c \
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$(MCU_DIR)/drivers/fsl_anatop_ai.c \
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$(MCU_DIR)/drivers/fsl_caam.c \
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$(MCU_DIR)/drivers/fsl_lpadc.c \
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$(MCU_DIR)/drivers/fsl_mu.c
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$(MCU_DIR)/drivers/fsl_soc_src.c \
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$(MCU_DIR)/drivers/fsl_gpc.c \
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$(MCUX_SDK_DIR)/drivers/caam/fsl_caam.c \
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$(MCUX_SDK_DIR)/drivers/lpadc/fsl_lpadc.c \
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$(MCUX_SDK_DIR)/drivers/mu/fsl_mu.c
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INC_HAL_IMX += \
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-I$(TOP)/$(MCU_DIR)/drivers/cm7 \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/caam \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/lpadc \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/mu
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CFLAGS += -DCACHE_MODE_WRITE_THROUGH=1
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else
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SRC_HAL_IMX_C += \
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$(MCU_DIR)/drivers/fsl_adc.c \
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$(MCU_DIR)/drivers/fsl_cache.c \
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$(MCU_DIR)/drivers/fsl_trng.c
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$(MCUX_SDK_DIR)/drivers/adc_12b1msps_sar/fsl_adc.c \
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$(MCUX_SDK_DIR)/drivers/cache/armv7-m7/fsl_cache.c \
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$(MCUX_SDK_DIR)/drivers/gpc_1/fsl_gpc.c \
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$(MCUX_SDK_DIR)/drivers/src/fsl_src.c \
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$(MCUX_SDK_DIR)/drivers/trng/fsl_trng.c
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INC_HAL_IMX += \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/adc_12b1msps_sar \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/cache/armv7-m7 \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/gpc_1 \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/src \
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-I$(TOP)/$(MCUX_SDK_DIR)/drivers/trng
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endif
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INC += $(INC_HAL_IMX)
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# C source files
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SRC_C += \
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board_init.c \
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@ -350,8 +394,6 @@ CFLAGS += \
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-DMICROPY_HW_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE) \
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-DMICROPY_HW_SDRAM_AVAIL=$(MICROPY_HW_SDRAM_AVAIL) \
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-DMICROPY_HW_SDRAM_SIZE=$(MICROPY_HW_SDRAM_SIZE) \
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-DSPI_RETRY_TIMES=1000000 \
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-DUART_RETRY_TIMES=1000000 \
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-DXIP_BOOT_HEADER_ENABLE=1 \
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-DXIP_EXTERNAL_FLASH=1 \
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-fdata-sections \
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@ -21,14 +21,14 @@
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#define MICROPY_HW_UART_INDEX { 1, 3, 2, 6, 8 }
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#define IOMUX_TABLE_UART \
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{ IOMUXC_GPIO_AD_B0_12_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RX }, \
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{ IOMUXC_GPIO_AD_B1_02_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RX }, \
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{ IOMUXC_GPIO_AD_B1_06_LPUART3_TX }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RX }, \
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{ IOMUXC_GPIO_AD_B0_12_LPUART1_TXD }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RXD }, \
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{ IOMUXC_GPIO_AD_B1_02_LPUART2_TXD }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RXD }, \
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{ IOMUXC_GPIO_AD_B1_06_LPUART3_TXD }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RXD }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ IOMUXC_GPIO_AD_B0_02_LPUART6_TX }, { IOMUXC_GPIO_AD_B0_03_LPUART6_RX }, \
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{ IOMUXC_GPIO_AD_B0_02_LPUART6_TXD }, { IOMUXC_GPIO_AD_B0_03_LPUART6_RXD }, \
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{ 0 }, { 0 }, \
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{ IOMUXC_GPIO_AD_B1_10_LPUART8_TX }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RX },
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{ IOMUXC_GPIO_AD_B1_10_LPUART8_TXD }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RXD },
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#define IOMUX_TABLE_UART_CTS_RTS \
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{ IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B }, { IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B }, \
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@ -111,22 +111,22 @@
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}
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// --- SEMC --- //
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#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DATA00
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#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DATA01
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#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DATA02
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#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DATA03
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#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DATA04
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#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DATA05
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#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DATA06
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#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DATA07
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#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_30_SEMC_DATA08
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#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_31_SEMC_DATA09
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#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_32_SEMC_DATA10
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#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_33_SEMC_DATA11
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#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_34_SEMC_DATA12
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#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_35_SEMC_DATA13
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#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_36_SEMC_DATA14
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#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_37_SEMC_DATA15
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#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DA00
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#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DA01
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#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DA02
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#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DA03
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#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DA04
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#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DA05
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#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DA06
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#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DA07
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#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_30_SEMC_DA08
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#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_31_SEMC_DA09
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#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_32_SEMC_DA10
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#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_33_SEMC_DA11
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#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_34_SEMC_DA12
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#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_35_SEMC_DA13
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#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_36_SEMC_DA14
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#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_37_SEMC_DA15
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#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_09_SEMC_ADDR00
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#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_10_SEMC_ADDR01
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@ -1,5 +1,5 @@
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/*
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* Copyright 2017-2019 NXP
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* Copyright 2022 NXP
|
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* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
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@ -22,11 +22,11 @@
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|||
|
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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||||
!!GlobalInfo
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||||
product: Clocks v5.0
|
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product: Clocks v10.0
|
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processor: MIMXRT1052xxxxB
|
||||
package_id: MIMXRT1052DVL6B
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.0.0
|
||||
processor_version: 0.12.10
|
||||
board: IMXRT1050-EVKB
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
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@ -40,8 +40,6 @@ board: IMXRT1050-EVKB
|
|||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
|
|
@ -64,7 +62,6 @@ outputs:
|
|||
- {id: CLK_1M.outFreq, value: 1 MHz}
|
||||
- {id: CLK_24M.outFreq, value: 24 MHz}
|
||||
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
|
||||
- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
|
||||
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
|
||||
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
|
||||
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
|
|
@ -92,7 +89,7 @@ outputs:
|
|||
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
|
||||
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
|
||||
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
|
||||
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
|
||||
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
|
||||
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
|
||||
|
|
@ -104,7 +101,7 @@ settings:
|
|||
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
|
||||
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.SEMC_PODF.scale, value: '8'}
|
||||
- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
|
||||
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
|
||||
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
|
||||
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
|
||||
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
|
||||
|
|
@ -125,31 +122,45 @@ settings:
|
|||
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
|
||||
- {id: CCM_ANALOG.PLL4.div, value: '47'}
|
||||
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
|
||||
- {id: CCM_ANALOG.PLL5.div, value: '40'}
|
||||
- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
|
||||
- {id: CCM_ANALOG.PLL5.num, value: '0'}
|
||||
- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
|
||||
- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
|
||||
- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
|
||||
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
|
||||
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
|
||||
- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
|
||||
sources:
|
||||
- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
|
||||
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
|
||||
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
|
||||
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
|
||||
.numerator = 0, /* 30 bit numerator of fractional loop divider */
|
||||
.denominator = 1, /* 30 bit denominator of fractional loop divider */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
|
||||
.numerator = 0, /* 30 bit numerator of fractional loop divider */
|
||||
.denominator = 1, /* 30 bit denominator of fractional loop divider */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
|
||||
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||
.postDivider = 8, /* Divider after PLL */
|
||||
.numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||
.denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
|
|
@ -213,10 +224,9 @@ void BOARD_BootClockRUN(void) {
|
|||
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
|
||||
/* Set Usdhc2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
|
||||
* unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
/* Disable Semc clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Semc);
|
||||
|
|
@ -227,10 +237,9 @@ void BOARD_BootClockRUN(void) {
|
|||
/* Set Semc clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 0);
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
|
||||
* unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Disable Flexspi clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_FlexSpi);
|
||||
|
|
@ -257,9 +266,9 @@ void BOARD_BootClockRUN(void) {
|
|||
/* Disable TRACE clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Trace);
|
||||
/* Set TRACE_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
|
||||
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
|
||||
/* Set Trace clock source. */
|
||||
CLOCK_SetMux(kCLOCK_TraceMux, 2);
|
||||
CLOCK_SetMux(kCLOCK_TraceMux, 0);
|
||||
/* Disable SAI1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai1);
|
||||
/* Set SAI1_CLK_PRED. */
|
||||
|
|
@ -351,10 +360,12 @@ void BOARD_BootClockRUN(void) {
|
|||
/* Init ARM PLL. */
|
||||
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
|
||||
* unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
|
||||
* well.*/
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
|
||||
#endif
|
||||
/* Init System PLL. */
|
||||
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
|
||||
/* Init System pfd0. */
|
||||
|
|
@ -365,13 +376,10 @@ void BOARD_BootClockRUN(void) {
|
|||
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
|
||||
/* Init System pfd3. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
|
||||
/* Disable pfd offset. */
|
||||
CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
|
||||
* unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
|
||||
* well.*/
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Init Usb1 PLL. */
|
||||
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
|
||||
|
|
@ -395,21 +403,30 @@ void BOARD_BootClockRUN(void) {
|
|||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
|
||||
/* Enable Audio PLL output. */
|
||||
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
|
||||
/* DeInit Video PLL. */
|
||||
CLOCK_DeinitVideoPll();
|
||||
/* Bypass Video PLL. */
|
||||
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
|
||||
/* Set divider for Video PLL. */
|
||||
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
|
||||
/* Enable Video PLL output. */
|
||||
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
|
||||
/* Init Video PLL. */
|
||||
uint32_t pllVideo;
|
||||
/* Disable Video PLL output before initial Video PLL. */
|
||||
CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
|
||||
/* Bypass PLL first */
|
||||
CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
|
||||
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
|
||||
CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
|
||||
CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
|
||||
pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
|
||||
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
|
||||
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
|
||||
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
|
||||
CCM_ANALOG->PLL_VIDEO = pllVideo;
|
||||
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) {
|
||||
}
|
||||
/* Disable bypass for Video PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
|
||||
/* DeInit Enet PLL. */
|
||||
CLOCK_DeinitEnetPll();
|
||||
/* Bypass Enet PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
|
||||
/* Set Enet output divider. */
|
||||
CCM_ANALOG->PLL_ENET =
|
||||
(CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
|
||||
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
|
||||
/* Enable Enet output. */
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
|
||||
/* Enable Enet25M output. */
|
||||
|
|
@ -429,8 +446,7 @@ void BOARD_BootClockRUN(void) {
|
|||
/* Set per clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
|
||||
/* Set lvds1 clock source. */
|
||||
CCM_ANALOG->MISC1 =
|
||||
(CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
|
||||
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
|
||||
/* Set clock out1 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
|
||||
/* Set clock out1 source. */
|
||||
|
|
@ -457,13 +473,19 @@ void BOARD_BootClockRUN(void) {
|
|||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
|
||||
/* Set MQS configuration. */
|
||||
IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
|
||||
/* Set ENET Tx clock source. */
|
||||
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
|
||||
/* Set ENET Ref clock source. */
|
||||
#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
|
||||
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
|
||||
#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
|
||||
/* Backward compatibility for original bitfield name */
|
||||
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
|
||||
#else
|
||||
#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
|
||||
#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
|
||||
/* Set GPT1 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
|
||||
/* Set GPT2 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
CLOCK_SetMode(kCLOCK_ModeRun);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2017-2019 NXP
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
@ -13,9 +13,9 @@
|
|||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
|
@ -40,54 +40,55 @@ void BOARD_InitBootClocks(void);
|
|||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
|
||||
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 40000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
|
||||
|
||||
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
|
|
@ -98,6 +99,9 @@ extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
|
|||
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
|
|
|
|||
|
|
@ -77,14 +77,14 @@
|
|||
|
||||
#define I2S_GPIO_MAP \
|
||||
{ \
|
||||
I2S_GPIO(1, MCK, TX, GPIO_08, IOMUXC_GPIO_08_SAI1_MCLK), /* pin D8 */ \
|
||||
I2S_GPIO(1, SCK, RX, GPIO_01, IOMUXC_GPIO_01_SAI1_RX_BCLK), /* pin D1 */ \
|
||||
I2S_GPIO(1, WS, RX, GPIO_02, IOMUXC_GPIO_02_SAI1_RX_SYNC), /* pin D2 */ \
|
||||
I2S_GPIO(1, SD, RX, GPIO_03, IOMUXC_GPIO_03_SAI1_RX_DATA00), /* pin D3 */ \
|
||||
I2S_GPIO(1, SCK, TX, GPIO_06, IOMUXC_GPIO_06_SAI1_TX_BCLK), /* pin D6 */ \
|
||||
I2S_GPIO(1, WS, TX, GPIO_07, IOMUXC_GPIO_07_SAI1_TX_SYNC), /* pin D7 */ \
|
||||
I2S_GPIO(1, SD, TX, GPIO_04, IOMUXC_GPIO_04_SAI1_TX_DATA00), /* pin D4 */ \
|
||||
I2S_GPIO(3, SCK, TX, GPIO_SD_01, IOMUXC_GPIO_SD_01_SAI3_TX_BCLK), /* pin D10 */ \
|
||||
I2S_GPIO(3, WS, TX, GPIO_SD_00, IOMUXC_GPIO_SD_00_SAI3_TX_SYNC), /* pin D9 */ \
|
||||
I2S_GPIO(3, SD, TX, GPIO_SD_02, IOMUXC_GPIO_SD_02_SAI3_TX_DATA) /* pin D11 */ \
|
||||
I2S_GPIO(1, MCK, TX, GPIO_08, IOMUXC_GPIO_08_SAI1_MCLK), /* pin D8 */ \
|
||||
I2S_GPIO(1, SCK, RX, GPIO_01, IOMUXC_GPIO_01_SAI1_RX_BCLK), /* pin D1 */ \
|
||||
I2S_GPIO(1, WS, RX, GPIO_02, IOMUXC_GPIO_02_SAI1_RX_SYNC), /* pin D2 */ \
|
||||
I2S_GPIO(1, SD, RX, GPIO_03, IOMUXC_GPIO_03_SAI1_RX_DATA00), /* pin D3 */ \
|
||||
I2S_GPIO(1, SCK, TX, GPIO_06, IOMUXC_GPIO_06_SAI1_TX_BCLK), /* pin D6 */ \
|
||||
I2S_GPIO(1, WS, TX, GPIO_07, IOMUXC_GPIO_07_SAI1_TX_SYNC), /* pin D7 */ \
|
||||
I2S_GPIO(1, SD, TX, GPIO_04, IOMUXC_GPIO_04_SAI1_TX_DATA00), /* pin D4 */ \
|
||||
I2S_GPIO(3, SCK, TX, GPIO_SD_01, IOMUXC_GPIO_SD_01_SAI3_TX_BCLK), /* pin D10 */ \
|
||||
I2S_GPIO(3, WS, TX, GPIO_SD_00, IOMUXC_GPIO_SD_00_SAI3_TX_SYNC), /* pin D9 */ \
|
||||
I2S_GPIO(3, SD, TX, GPIO_SD_02, IOMUXC_GPIO_SD_02_SAI3_TX_DATA) /* pin D11 */ \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -23,14 +23,14 @@
|
|||
#define MICROPY_HW_UART_INDEX { 0, 1, 2, 3, 8, 4 }
|
||||
|
||||
#define IOMUX_TABLE_UART \
|
||||
{ IOMUXC_GPIO_AD_B0_12_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RX }, \
|
||||
{ IOMUXC_GPIO_AD_B1_02_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RX }, \
|
||||
{ IOMUXC_GPIO_AD_B1_06_LPUART3_TX }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RX }, \
|
||||
{ IOMUXC_GPIO_B1_00_LPUART4_TX }, { IOMUXC_GPIO_B1_01_LPUART4_RX }, \
|
||||
{ IOMUXC_GPIO_AD_B0_12_LPUART1_TXD }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RXD }, \
|
||||
{ IOMUXC_GPIO_AD_B1_02_LPUART2_TXD }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RXD }, \
|
||||
{ IOMUXC_GPIO_AD_B1_06_LPUART3_TXD }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RXD }, \
|
||||
{ IOMUXC_GPIO_B1_00_LPUART4_TXD }, { IOMUXC_GPIO_B1_01_LPUART4_RXD }, \
|
||||
{ 0 }, { 0 }, \
|
||||
{ 0 }, { 0 }, \
|
||||
{ 0 }, { 0 }, \
|
||||
{ IOMUXC_GPIO_AD_B1_10_LPUART8_TX }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RX },
|
||||
{ IOMUXC_GPIO_AD_B1_10_LPUART8_TXD }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RXD },
|
||||
|
||||
#define IOMUX_TABLE_UART_CTS_RTS \
|
||||
{ IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B }, { IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B }, \
|
||||
|
|
@ -98,13 +98,13 @@
|
|||
|
||||
#define I2S_GPIO_MAP \
|
||||
{ \
|
||||
I2S_GPIO(1, MCK, TX, GPIO_AD_B1_09, IOMUXC_GPIO_AD_B1_09_SAI1_MCLK), /* pin J4 09 */ \
|
||||
I2S_GPIO(1, SCK, RX, GPIO_AD_B1_11, IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK), /* pin J4 11 */ \
|
||||
I2S_GPIO(1, WS, RX, GPIO_AD_B1_10, IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC), /* pin J4 10 */ \
|
||||
I2S_GPIO(1, SD, RX, GPIO_AD_B1_12, IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00), /* pin J4 12 */ \
|
||||
I2S_GPIO(1, SCK, TX, GPIO_AD_B1_14, IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK), /* pin J4 14 */ \
|
||||
I2S_GPIO(1, WS, TX, GPIO_AD_B1_15, IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC), /* pin J4 15 */ \
|
||||
I2S_GPIO(1, SD, TX, GPIO_AD_B1_13, IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00) /* pin J4 13 */ \
|
||||
I2S_GPIO(1, MCK, TX, GPIO_AD_B1_09, IOMUXC_GPIO_AD_B1_09_SAI1_MCLK), /* pin J4 09 */ \
|
||||
I2S_GPIO(1, SCK, RX, GPIO_AD_B1_11, IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK), /* pin J4 11 */ \
|
||||
I2S_GPIO(1, WS, RX, GPIO_AD_B1_10, IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC), /* pin J4 10 */ \
|
||||
I2S_GPIO(1, SD, RX, GPIO_AD_B1_12, IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00), /* pin J4 12 */ \
|
||||
I2S_GPIO(1, SCK, TX, GPIO_AD_B1_14, IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK), /* pin J4 14 */ \
|
||||
I2S_GPIO(1, WS, TX, GPIO_AD_B1_15, IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC), /* pin J4 15 */ \
|
||||
I2S_GPIO(1, SD, TX, GPIO_AD_B1_13, IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00) /* pin J4 13 */ \
|
||||
}
|
||||
|
||||
#define USDHC_DUMMY_PIN NULL, 0
|
||||
|
|
@ -140,22 +140,22 @@
|
|||
{ IOMUXC_GPIO_EMC_40_ENET_MDC, 0, 0xB0E9u },
|
||||
|
||||
// --- SEMC --- //
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DATA00
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DATA01
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DATA02
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DATA03
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DATA04
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DATA05
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DATA06
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DATA07
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_30_SEMC_DATA08
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_31_SEMC_DATA09
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_32_SEMC_DATA10
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_33_SEMC_DATA11
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_34_SEMC_DATA12
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_35_SEMC_DATA13
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_36_SEMC_DATA14
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_37_SEMC_DATA15
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DA00
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DA01
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DA02
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DA03
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DA04
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DA05
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DA06
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DA07
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_30_SEMC_DA08
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_31_SEMC_DA09
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_32_SEMC_DA10
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_33_SEMC_DA11
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_34_SEMC_DA12
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_35_SEMC_DA13
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_36_SEMC_DA14
|
||||
#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_37_SEMC_DA15
|
||||
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_09_SEMC_ADDR00
|
||||
#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_10_SEMC_ADDR01
|
||||
|
|
|
|||
|
|
@ -14,4 +14,3 @@ MICROPY_SSL_MBEDTLS = 1
|
|||
|
||||
FROZEN_MANIFEST ?= $(BOARD_DIR)/manifest.py
|
||||
|
||||
CFLAGS += -DSPI_RETRY_TIMES=1000000
|
||||
|
|
|
|||
|
|
@ -89,19 +89,19 @@
|
|||
|
||||
#define I2S_GPIO_MAP \
|
||||
{ \
|
||||
I2S_GPIO(1, SCK, RX, GPIO_AD_B1_11, IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK), /* pin 21 */ \
|
||||
I2S_GPIO(1, WS, RX, GPIO_AD_B1_10, IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC), /* pin 20 */ \
|
||||
I2S_GPIO(1, SD, RX, GPIO_B1_00, IOMUXC_GPIO_B1_00_SAI1_RX_DATA00), /* pin 8 */ \
|
||||
I2S_GPIO(1, SCK, TX, GPIO_AD_B1_14, IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK), /* pin 26 */ \
|
||||
I2S_GPIO(1, SCK, TX, GPIO_B1_02, IOMUXC_GPIO_B1_02_SAI1_TX_BCLK), /* pin 36 */ \
|
||||
I2S_GPIO(1, WS, TX, GPIO_AD_B1_15, IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC), /* pin 27 */ \
|
||||
I2S_GPIO(1, WS, TX, GPIO_B1_03, IOMUXC_GPIO_B1_03_SAI1_TX_SYNC), /* pin 37 */ \
|
||||
I2S_GPIO(1, SD, TX, GPIO_B1_01, IOMUXC_GPIO_B1_01_SAI1_TX_DATA00), /* pin 7 */ \
|
||||
I2S_GPIO(1, MCK, TX, GPIO_AD_B1_09, IOMUXC_GPIO_AD_B1_09_SAI1_MCLK), /* pin 23 */ \
|
||||
I2S_GPIO(2, SCK, TX, GPIO_EMC_06, IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK), /* pin 4 */ \
|
||||
I2S_GPIO(2, WS, TX, GPIO_EMC_05, IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC), /* pin 3 */ \
|
||||
I2S_GPIO(2, SD, TX, GPIO_EMC_04, IOMUXC_GPIO_EMC_04_SAI2_TX_DATA), /* pin 2 */ \
|
||||
I2S_GPIO(2, MCK, TX, GPIO_EMC_07, IOMUXC_GPIO_EMC_07_SAI2_MCLK) /* pin 33 */ \
|
||||
I2S_GPIO(1, SCK, RX, GPIO_AD_B1_11, IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK), /* pin 21 */ \
|
||||
I2S_GPIO(1, WS, RX, GPIO_AD_B1_10, IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC), /* pin 20 */ \
|
||||
I2S_GPIO(1, SD, RX, GPIO_B1_00, IOMUXC_GPIO_B1_00_SAI1_RX_DATA00), /* pin 8 */ \
|
||||
I2S_GPIO(1, SCK, TX, GPIO_AD_B1_14, IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK), /* pin 26 */ \
|
||||
I2S_GPIO(1, SCK, TX, GPIO_B1_02, IOMUXC_GPIO_B1_02_SAI1_TX_BCLK), /* pin 36 */ \
|
||||
I2S_GPIO(1, WS, TX, GPIO_AD_B1_15, IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC), /* pin 27 */ \
|
||||
I2S_GPIO(1, WS, TX, GPIO_B1_03, IOMUXC_GPIO_B1_03_SAI1_TX_SYNC), /* pin 37 */ \
|
||||
I2S_GPIO(1, SD, TX, GPIO_B1_01, IOMUXC_GPIO_B1_01_SAI1_TX_DATA00), /* pin 7 */ \
|
||||
I2S_GPIO(1, MCK, TX, GPIO_AD_B1_09, IOMUXC_GPIO_AD_B1_09_SAI1_MCLK), /* pin 23 */ \
|
||||
I2S_GPIO(2, SCK, TX, GPIO_EMC_06, IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK), /* pin 4 */ \
|
||||
I2S_GPIO(2, WS, TX, GPIO_EMC_05, IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC), /* pin 3 */ \
|
||||
I2S_GPIO(2, SD, TX, GPIO_EMC_04, IOMUXC_GPIO_EMC_04_SAI2_TX_DATA), /* pin 2 */ \
|
||||
I2S_GPIO(2, MCK, TX, GPIO_EMC_07, IOMUXC_GPIO_EMC_07_SAI2_MCLK) /* pin 33 */ \
|
||||
}
|
||||
|
||||
#define USDHC_DUMMY_PIN NULL, 0
|
||||
|
|
|
|||
|
|
@ -91,21 +91,21 @@
|
|||
|
||||
#define I2S_GPIO_MAP \
|
||||
{ \
|
||||
I2S_GPIO(1, SCK, RX, GPIO_AD_B1_11, IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK), /* pin 21 */ \
|
||||
I2S_GPIO(1, WS, RX, GPIO_AD_B1_10, IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC), /* pin 20 */ \
|
||||
I2S_GPIO(1, SD, RX, GPIO_AD_B1_12, IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00), /* pin 38 */ \
|
||||
I2S_GPIO(1, SD, RX, GPIO_B1_00, IOMUXC_GPIO_B1_00_SAI1_RX_DATA00), /* pin 8 */ \
|
||||
I2S_GPIO(1, SCK, TX, GPIO_AD_B1_14, IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK), /* pin 26 */ \
|
||||
I2S_GPIO(1, SCK, TX, GPIO_B1_02, IOMUXC_GPIO_B1_02_SAI1_TX_BCLK), /* pin 36 */ \
|
||||
I2S_GPIO(1, WS, TX, GPIO_AD_B1_15, IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC), /* pin 27 */ \
|
||||
I2S_GPIO(1, WS, TX, GPIO_B1_03, IOMUXC_GPIO_B1_03_SAI1_TX_SYNC), /* pin 37 */ \
|
||||
I2S_GPIO(1, SD, TX, GPIO_AD_B1_13, IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00), /* pin 39 */ \
|
||||
I2S_GPIO(1, SD, TX, GPIO_B1_01, IOMUXC_GPIO_B1_01_SAI1_TX_DATA00), /* pin 7 */ \
|
||||
I2S_GPIO(1, MCK, TX, GPIO_AD_B1_09, IOMUXC_GPIO_AD_B1_09_SAI1_MCLK), /* pin 23 */ \
|
||||
I2S_GPIO(2, SCK, TX, GPIO_EMC_06, IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK), /* pin 4 */ \
|
||||
I2S_GPIO(2, WS, TX, GPIO_EMC_05, IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC), /* pin 3 */ \
|
||||
I2S_GPIO(2, SD, TX, GPIO_EMC_04, IOMUXC_GPIO_EMC_04_SAI2_TX_DATA), /* pin 2 */ \
|
||||
I2S_GPIO(2, MCK, TX, GPIO_EMC_07, IOMUXC_GPIO_EMC_07_SAI2_MCLK) /* pin 33 */ \
|
||||
I2S_GPIO(1, SCK, RX, GPIO_AD_B1_11, IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK), /* pin 21 */ \
|
||||
I2S_GPIO(1, WS, RX, GPIO_AD_B1_10, IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC), /* pin 20 */ \
|
||||
I2S_GPIO(1, SD, RX, GPIO_AD_B1_12, IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00), /* pin 38 */ \
|
||||
I2S_GPIO(1, SD, RX, GPIO_B1_00, IOMUXC_GPIO_B1_00_SAI1_RX_DATA00), /* pin 8 */ \
|
||||
I2S_GPIO(1, SCK, TX, GPIO_AD_B1_14, IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK), /* pin 26 */ \
|
||||
I2S_GPIO(1, SCK, TX, GPIO_B1_02, IOMUXC_GPIO_B1_02_SAI1_TX_BCLK), /* pin 36 */ \
|
||||
I2S_GPIO(1, WS, TX, GPIO_AD_B1_15, IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC), /* pin 27 */ \
|
||||
I2S_GPIO(1, WS, TX, GPIO_B1_03, IOMUXC_GPIO_B1_03_SAI1_TX_SYNC), /* pin 37 */ \
|
||||
I2S_GPIO(1, SD, TX, GPIO_AD_B1_13, IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00), /* pin 39 */ \
|
||||
I2S_GPIO(1, SD, TX, GPIO_B1_01, IOMUXC_GPIO_B1_01_SAI1_TX_DATA00), /* pin 7 */ \
|
||||
I2S_GPIO(1, MCK, TX, GPIO_AD_B1_09, IOMUXC_GPIO_AD_B1_09_SAI1_MCLK), /* pin 23 */ \
|
||||
I2S_GPIO(2, SCK, TX, GPIO_EMC_06, IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK), /* pin 4 */ \
|
||||
I2S_GPIO(2, WS, TX, GPIO_EMC_05, IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC), /* pin 3 */ \
|
||||
I2S_GPIO(2, SD, TX, GPIO_EMC_04, IOMUXC_GPIO_EMC_04_SAI2_TX_DATA), /* pin 2 */ \
|
||||
I2S_GPIO(2, MCK, TX, GPIO_EMC_07, IOMUXC_GPIO_EMC_07_SAI2_MCLK) /* pin 33 */ \
|
||||
}
|
||||
|
||||
#define USDHC_DUMMY_PIN NULL, 0
|
||||
|
|
|
|||
|
|
@ -397,9 +397,11 @@ void eth_init_0(eth_t *self, int eth_id, const phy_operations_t *phy_ops, int ph
|
|||
enet_config.txAccelerConfig = kENET_TxAccelIpCheckEnabled | kENET_TxAccelProtoCheckEnabled;
|
||||
// Set interrupt
|
||||
enet_config.interrupt |= ENET_TX_INTERRUPT | ENET_RX_INTERRUPT;
|
||||
// Set callback
|
||||
enet_config.callback = eth_irq_handler;
|
||||
enet_config.userData = (void *)self;
|
||||
|
||||
ENET_Init(ENET, &g_handle, &enet_config, &buffConfig[0], hw_addr, source_clock);
|
||||
ENET_SetCallback(&g_handle, eth_irq_handler, (void *)self);
|
||||
NVIC_SetPriority(ENET_IRQn, IRQ_PRI_PENDSV);
|
||||
ENET_EnableInterrupts(ENET, ENET_RX_INTERRUPT);
|
||||
ENET_ClearInterruptStatus(ENET, ENET_TX_INTERRUPT | ENET_RX_INTERRUPT | ENET_ERR_INTERRUPT);
|
||||
|
|
@ -461,9 +463,11 @@ void eth_init_1(eth_t *self, int eth_id, const phy_operations_t *phy_ops, int ph
|
|||
enet_config.txAccelerConfig = kENET_TxAccelIpCheckEnabled | kENET_TxAccelProtoCheckEnabled;
|
||||
// Set interrupt
|
||||
enet_config.interrupt = ENET_TX_INTERRUPT | ENET_RX_INTERRUPT;
|
||||
// Set callback
|
||||
enet_config.callback = eth_irq_handler;
|
||||
enet_config.userData = (void *)self;
|
||||
|
||||
ENET_Init(ENET_1, &g_handle_1, &enet_config, &buffConfig_1[0], hw_addr_1, source_clock);
|
||||
ENET_SetCallback(&g_handle_1, eth_irq_handler, (void *)self);
|
||||
ENET_ClearInterruptStatus(ENET_1, ENET_TX_INTERRUPT | ENET_RX_INTERRUPT | ENET_ERR_INTERRUPT);
|
||||
ENET_EnableInterrupts(ENET_1, ENET_RX_INTERRUPT);
|
||||
ENET_ActiveRead(ENET_1);
|
||||
|
|
|
|||
|
|
@ -538,14 +538,14 @@ static bool i2s_init(machine_i2s_obj_t *self) {
|
|||
EDMA_PrepareTransfer(&transferConfig,
|
||||
self->dma_buffer_dcache_aligned, bytes_per_sample,
|
||||
(void *)destAddr, bytes_per_sample,
|
||||
(FSL_FEATURE_SAI_FIFO_COUNT - saiConfig.fifo.fifoWatermark) * bytes_per_sample,
|
||||
(FSL_FEATURE_SAI_FIFO_COUNTn(self->i2s_inst) - saiConfig.fifo.fifoWatermark) * bytes_per_sample,
|
||||
SIZEOF_DMA_BUFFER_IN_BYTES, kEDMA_MemoryToPeripheral);
|
||||
} else { // RX
|
||||
uint32_t srcAddr = SAI_RxGetDataRegisterAddress(self->i2s_inst, SAI_CHANNEL_0);
|
||||
EDMA_PrepareTransfer(&transferConfig,
|
||||
(void *)srcAddr, bytes_per_sample,
|
||||
self->dma_buffer_dcache_aligned, bytes_per_sample,
|
||||
(FSL_FEATURE_SAI_FIFO_COUNT - saiConfig.fifo.fifoWatermark) * bytes_per_sample,
|
||||
(FSL_FEATURE_SAI_FIFO_COUNTn(self->i2s_inst) - saiConfig.fifo.fifoWatermark) * bytes_per_sample,
|
||||
SIZEOF_DMA_BUFFER_IN_BYTES, kEDMA_PeripheralToMemory);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -239,7 +239,6 @@ static void configure_flexpwm(machine_pwm_obj_t *self) {
|
|||
pwmConfig.pairOperation = kPWM_Independent;
|
||||
}
|
||||
pwmConfig.clockSource = kPWM_BusClock;
|
||||
pwmConfig.enableWait = false;
|
||||
pwmConfig.initializationControl = self->sync ? kPWM_Initialize_MasterSync : kPWM_Initialize_LocalSync;
|
||||
|
||||
if (PWM_Init(self->instance, self->submodule, &pwmConfig) == kStatus_Fail) {
|
||||
|
|
|
|||
|
|
@ -157,7 +157,9 @@ void machine_rtc_start(void) {
|
|||
// Do a basic init.
|
||||
SNVS_LP_Init(SNVS);
|
||||
// Disable all external Tamper
|
||||
#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 0)
|
||||
SNVS_LP_DisableAllExternalTamper(SNVS);
|
||||
#endif
|
||||
|
||||
SNVS_LP_SRTC_StartTimer(SNVS);
|
||||
// If the date is not set, set it to a more recent start date,
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
// Board specific definitions
|
||||
#include "mpconfigboard.h"
|
||||
#include "fsl_common.h"
|
||||
#include "lib/nxp_driver/sdk/CMSIS/Include/core_cm7.h"
|
||||
#include "lib/cmsis/inc/core_cm7.h"
|
||||
|
||||
uint32_t trng_random_u32(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ function ci_code_size_setup {
|
|||
function ci_code_size_build {
|
||||
# check the following ports for the change in their code size
|
||||
PORTS_TO_CHECK=bmusxpd
|
||||
SUBMODULES="lib/asf4 lib/berkeley-db-1.xx lib/mbedtls lib/micropython-lib lib/nxp_driver lib/pico-sdk lib/stm32lib lib/tinyusb"
|
||||
SUBMODULES="lib/asf4 lib/berkeley-db-1.xx lib/mbedtls lib/micropython-lib lib/mcux-sdk lib/pico-sdk lib/stm32lib lib/tinyusb"
|
||||
|
||||
# starts off at either the ref/pull/N/merge FETCH_HEAD, or the current branch HEAD
|
||||
git checkout -b pull_request # save the current location
|
||||
|
|
@ -206,6 +206,12 @@ function ci_mimxrt_build {
|
|||
make ${MAKEOPTS} -C ports/mimxrt BOARD=MIMXRT1020_EVK
|
||||
make ${MAKEOPTS} -C ports/mimxrt BOARD=TEENSY40 submodules
|
||||
make ${MAKEOPTS} -C ports/mimxrt BOARD=TEENSY40
|
||||
make ${MAKEOPTS} -C ports/mimxrt BOARD=MIMXRT1050_EVK submodules
|
||||
make ${MAKEOPTS} -C ports/mimxrt BOARD=MIMXRT1050_EVK
|
||||
make ${MAKEOPTS} -C ports/mimxrt BOARD=MIMXRT1060_EVK submodules
|
||||
make ${MAKEOPTS} -C ports/mimxrt BOARD=MIMXRT1060_EVK
|
||||
make ${MAKEOPTS} -C ports/mimxrt BOARD=MIMXRT1170_EVK submodules
|
||||
make ${MAKEOPTS} -C ports/mimxrt BOARD=MIMXRT1170_EVK
|
||||
}
|
||||
|
||||
########################################################################################
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue