kopia lustrzana https://github.com/micropython/micropython
stm32/fdcan: Fix FIFO1 usage and handling of error interrupts.
The original code used a independent state with regards to the interrupt. During heavy bus error conditions the internal state could become out-of-sync with the interrupts. Further explanation: during the development of an application using CAN communication, a interrupt-run-away was found in some situations. It was found that the error interrupt triggered (Warning, Passive or Bus-Off, all triggered it) the run-away. The only recovery was a reset. Two problems were found: - the error interrupt is enabled but not cleared in the interrupt routine; - an internal variable 'State' that was used to track the message received state (empty, new, full, overflow) that was not directly related to interrupt that indicated the state. In this commit these issues are fixed by adding more values for the interrupt reason (warning, passive, bus off) and clearing the error interrupts, and making the internal state directly dependent on the interrupt state for received messages. Furthermore, introducing the FIFO1 in the CAN receive stage, another issue existed. Even if the messages are received into the FIFO1 (by selecting message filtering for FIFO0 and FIFO1), the interrupt firing was indicating FIFO0 Rx. The configuration of the interrupts for this is now also fixed. The CAN peripheral has 2 interrupt lines going into the NVIC controller. The assignment of the interrupt reasons to these 2 interrupt lines was missing. Now the reception of FIFO1 messages triggers the second interrupt line. Other interrupts (Rx FIFO0 and bus error) are assigned to the first interrupt line. Tested on a Nucleo-G474, and also checked the HAL function to work with the H7 family.pull/8215/head
Herwin Grobben
Damien George
rodzic
a00e1e5735
commit
160e4d9a6d
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@ -44,6 +44,13 @@
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#define FDCAN_ELEMENT_MASK_FIDX (0x7f000000) // Filter Index
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#define FDCAN_ELEMENT_MASK_ANMF (0x80000000) // Accepted Non-matching Frame
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#define FDCAN_RX_FIFO0_MASK (FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST | FDCAN_FLAG_RX_FIFO0_FULL | FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE)
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#define FDCAN_RX_FIFO1_MASK (FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST | FDCAN_FLAG_RX_FIFO1_FULL | FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE)
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#define FDCAN_ERROR_STATUS_MASK (FDCAN_FLAG_ERROR_PASSIVE | FDCAN_FLAG_ERROR_WARNING | FDCAN_FLAG_BUS_OFF)
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// also defined in <PROC>_hal_fdcan.c, but not able to declare extern and reach the variable
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static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
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bool can_init(pyb_can_obj_t *can_obj, uint32_t mode, uint32_t prescaler, uint32_t sjw, uint32_t bs1, uint32_t bs2, bool auto_restart) {
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(void)auto_restart;
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@ -60,6 +67,16 @@ bool can_init(pyb_can_obj_t *can_obj, uint32_t mode, uint32_t prescaler, uint32_
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init->TransmitPause = DISABLE;
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init->ProtocolException = ENABLE;
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#if defined(STM32G4)
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init->ClockDivider = FDCAN_CLOCK_DIV1;
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init->DataPrescaler = 1;
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init->DataSyncJumpWidth = 1;
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init->DataTimeSeg1 = 1;
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init->DataTimeSeg2 = 1;
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#endif
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#if defined(STM32H7)
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// variable used to specify RAM address in HAL, only for H7, G4 uses defined offset address in HAL
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// The Message RAM is shared between CAN1 and CAN2. Setting the offset to half
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// the Message RAM for the second CAN and using half the resources for each CAN.
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if (can_obj->can_id == PYB_CAN_1) {
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@ -67,6 +84,14 @@ bool can_init(pyb_can_obj_t *can_obj, uint32_t mode, uint32_t prescaler, uint32_
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} else {
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init->MessageRAMOffset = 2560 / 2;
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}
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#endif
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#if defined(STM32G4)
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init->StdFiltersNbr = 28; // /2 ? if FDCAN2 is used !!?
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init->ExtFiltersNbr = 0; // Not used
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#elif defined(STM32H7)
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init->StdFiltersNbr = 64; // 128 / 2
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init->ExtFiltersNbr = 0; // Not used
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@ -83,6 +108,9 @@ bool can_init(pyb_can_obj_t *can_obj, uint32_t mode, uint32_t prescaler, uint32_
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init->TxFifoQueueElmtsNbr = 16; // Tx fifo elements
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init->TxElmtSize = FDCAN_DATA_BYTES_8;
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#endif
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init->TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
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FDCAN_GlobalTypeDef *CANx = NULL;
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@ -148,21 +176,27 @@ bool can_init(pyb_can_obj_t *can_obj, uint32_t mode, uint32_t prescaler, uint32_
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NVIC_SetPriority(FDCAN1_IT1_IRQn, IRQ_PRI_CAN);
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HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
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break;
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#if defined(MICROPY_HW_CAN2_TX)
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case PYB_CAN_2:
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NVIC_SetPriority(FDCAN2_IT0_IRQn, IRQ_PRI_CAN);
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HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
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NVIC_SetPriority(FDCAN2_IT1_IRQn, IRQ_PRI_CAN);
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HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
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break;
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#endif
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default:
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return false;
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}
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// FDCAN IT 0
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HAL_FDCAN_ConfigInterruptLines(&can_obj->can, FDCAN_IT_GROUP_RX_FIFO0 | FDCAN_IT_GROUP_BIT_LINE_ERROR | FDCAN_IT_GROUP_PROTOCOL_ERROR, FDCAN_INTERRUPT_LINE0);
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// FDCAN IT 1
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HAL_FDCAN_ConfigInterruptLines(&can_obj->can, FDCAN_IT_GROUP_RX_FIFO1, FDCAN_INTERRUPT_LINE1);
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__HAL_FDCAN_ENABLE_IT(&can_obj->can, FDCAN_IT_BUS_OFF | FDCAN_IT_ERROR_WARNING | FDCAN_IT_ERROR_PASSIVE);
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__HAL_FDCAN_ENABLE_IT(&can_obj->can, FDCAN_IT_RX_FIFO0_NEW_MESSAGE | FDCAN_IT_RX_FIFO1_NEW_MESSAGE);
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__HAL_FDCAN_ENABLE_IT(&can_obj->can, FDCAN_IT_RX_FIFO0_MESSAGE_LOST | FDCAN_IT_RX_FIFO1_MESSAGE_LOST);
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__HAL_FDCAN_ENABLE_IT(&can_obj->can, FDCAN_IT_RX_FIFO0_FULL | FDCAN_IT_RX_FIFO1_FULL);
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uint32_t ActiveITs = FDCAN_IT_BUS_OFF | FDCAN_IT_ERROR_WARNING | FDCAN_IT_ERROR_PASSIVE;
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ActiveITs |= FDCAN_IT_RX_FIFO0_NEW_MESSAGE | FDCAN_IT_RX_FIFO1_NEW_MESSAGE;
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ActiveITs |= FDCAN_IT_RX_FIFO0_MESSAGE_LOST | FDCAN_IT_RX_FIFO1_MESSAGE_LOST;
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ActiveITs |= FDCAN_IT_RX_FIFO0_FULL | FDCAN_IT_RX_FIFO1_FULL;
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HAL_FDCAN_ActivateNotification(&can_obj->can, ActiveITs, 0);
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return true;
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}
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@ -227,10 +261,19 @@ int can_receive(FDCAN_HandleTypeDef *can, int fifo, FDCAN_RxHeaderTypeDef *hdr,
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uint32_t index, *address;
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if (fifo == FDCAN_RX_FIFO0) {
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index = (*rxf & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos;
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#if defined(STM32G4)
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address = (uint32_t *)(can->msgRam.RxFIFO0SA + (index * (18U * 4U))); // SRAMCAN_RF0_SIZE bytes, size not configurable
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#else
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address = (uint32_t *)(can->msgRam.RxFIFO0SA + (index * can->Init.RxFifo0ElmtSize * 4));
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#endif
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} else {
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index = (*rxf & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos;
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#if defined(STM32G4)
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// ToDo: test FIFO1, FIFO 0 is ok
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address = (uint32_t *)(can->msgRam.RxFIFO1SA + (index * (18U * 4U))); // SRAMCAN_RF1_SIZE bytes, size not configurable
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#else
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address = (uint32_t *)(can->msgRam.RxFIFO1SA + (index * can->Init.RxFifo1ElmtSize * 4));
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#endif
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}
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// Parse header of message
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@ -251,7 +294,7 @@ int can_receive(FDCAN_HandleTypeDef *can, int fifo, FDCAN_RxHeaderTypeDef *hdr,
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// Copy data
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uint8_t *pdata = (uint8_t *)address;
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for (uint32_t i = 0; i < 8; ++i) { // TODO use DLCtoBytes[hdr->DataLength] for length > 8
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for (uint32_t i = 0; i < DLCtoBytes[hdr->DataLength]; ++i) {
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*data++ = *pdata++;
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}
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@ -269,41 +312,97 @@ STATIC void can_rx_irq_handler(uint can_id, uint fifo_id) {
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self = MP_STATE_PORT(pyb_can_obj_all)[can_id - 1];
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CAN_TypeDef *can = self->can.Instance;
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uint32_t RxFifo0ITs;
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uint32_t RxFifo1ITs;
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// uint32_t Errors;
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uint32_t ErrorStatusITs;
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uint32_t Psr;
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RxFifo0ITs = can->IR & FDCAN_RX_FIFO0_MASK;
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RxFifo0ITs &= can->IE;
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RxFifo1ITs = can->IR & FDCAN_RX_FIFO1_MASK;
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RxFifo1ITs &= can->IE;
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// Errors = (&self->can)->Instance->IR & FDCAN_ERROR_MASK;
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// Errors &= (&self->can)->Instance->IE;
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ErrorStatusITs = can->IR & FDCAN_ERROR_STATUS_MASK;
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ErrorStatusITs &= can->IE;
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Psr = can->PSR;
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if (fifo_id == FDCAN_RX_FIFO0) {
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callback = self->rxcallback0;
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state = &self->rx_state0;
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if (RxFifo0ITs & FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE) {
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__HAL_FDCAN_DISABLE_IT(&self->can, FDCAN_IT_RX_FIFO0_NEW_MESSAGE);
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__HAL_FDCAN_CLEAR_FLAG(&self->can, FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE);
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irq_reason = MP_OBJ_NEW_SMALL_INT(0);
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*state = RX_STATE_MESSAGE_PENDING;
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}
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if (RxFifo0ITs & FDCAN_FLAG_RX_FIFO0_FULL) {
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__HAL_FDCAN_DISABLE_IT(&self->can, FDCAN_IT_RX_FIFO0_FULL);
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__HAL_FDCAN_CLEAR_FLAG(&self->can, FDCAN_FLAG_RX_FIFO0_FULL);
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irq_reason = MP_OBJ_NEW_SMALL_INT(1);
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*state = RX_STATE_FIFO_FULL;
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}
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if (RxFifo0ITs & FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST) {
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__HAL_FDCAN_DISABLE_IT(&self->can, FDCAN_IT_RX_FIFO0_MESSAGE_LOST);
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__HAL_FDCAN_CLEAR_FLAG(&self->can, FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST);
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irq_reason = MP_OBJ_NEW_SMALL_INT(2);
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*state = RX_STATE_FIFO_OVERFLOW;
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}
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} else {
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callback = self->rxcallback1;
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state = &self->rx_state1;
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}
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switch (*state) {
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case RX_STATE_FIFO_EMPTY:
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__HAL_FDCAN_DISABLE_IT(&self->can, (fifo_id == FDCAN_RX_FIFO0) ?
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FDCAN_IT_RX_FIFO0_NEW_MESSAGE : FDCAN_IT_RX_FIFO1_NEW_MESSAGE);
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if (RxFifo1ITs & FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE) {
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__HAL_FDCAN_DISABLE_IT(&self->can, FDCAN_IT_RX_FIFO1_NEW_MESSAGE);
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__HAL_FDCAN_CLEAR_FLAG(&self->can, FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE);
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irq_reason = MP_OBJ_NEW_SMALL_INT(0);
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*state = RX_STATE_MESSAGE_PENDING;
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break;
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case RX_STATE_MESSAGE_PENDING:
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__HAL_FDCAN_DISABLE_IT(&self->can, (fifo_id == FDCAN_RX_FIFO0) ? FDCAN_IT_RX_FIFO0_FULL : FDCAN_IT_RX_FIFO1_FULL);
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__HAL_FDCAN_CLEAR_FLAG(&self->can, (fifo_id == FDCAN_RX_FIFO0) ? FDCAN_FLAG_RX_FIFO0_FULL : FDCAN_FLAG_RX_FIFO1_FULL);
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}
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if (RxFifo1ITs & FDCAN_FLAG_RX_FIFO1_FULL) {
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__HAL_FDCAN_DISABLE_IT(&self->can, FDCAN_IT_RX_FIFO1_FULL);
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__HAL_FDCAN_CLEAR_FLAG(&self->can, FDCAN_FLAG_RX_FIFO1_FULL);
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irq_reason = MP_OBJ_NEW_SMALL_INT(1);
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*state = RX_STATE_FIFO_FULL;
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break;
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case RX_STATE_FIFO_FULL:
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__HAL_FDCAN_DISABLE_IT(&self->can, (fifo_id == FDCAN_RX_FIFO0) ?
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FDCAN_IT_RX_FIFO0_MESSAGE_LOST : FDCAN_IT_RX_FIFO1_MESSAGE_LOST);
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__HAL_FDCAN_CLEAR_FLAG(&self->can, (fifo_id == FDCAN_RX_FIFO0) ?
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FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST : FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST);
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}
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if (RxFifo1ITs & FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST) {
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__HAL_FDCAN_DISABLE_IT(&self->can, FDCAN_IT_RX_FIFO1_MESSAGE_LOST);
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__HAL_FDCAN_CLEAR_FLAG(&self->can, FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST);
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irq_reason = MP_OBJ_NEW_SMALL_INT(2);
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*state = RX_STATE_FIFO_OVERFLOW;
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break;
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case RX_STATE_FIFO_OVERFLOW:
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// This should never happen
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break;
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}
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}
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if (ErrorStatusITs & FDCAN_FLAG_ERROR_WARNING) {
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__HAL_FDCAN_CLEAR_FLAG(&self->can, FDCAN_FLAG_ERROR_WARNING);
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if (Psr & FDCAN_PSR_EW) {
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irq_reason = MP_OBJ_NEW_SMALL_INT(3);
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// mp_printf(MICROPY_ERROR_PRINTER, "clear warning %08x\n", (can->IR & FDCAN_ERROR_STATUS_MASK));
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}
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}
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if (ErrorStatusITs & FDCAN_FLAG_ERROR_PASSIVE) {
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__HAL_FDCAN_CLEAR_FLAG(&self->can, FDCAN_FLAG_ERROR_PASSIVE);
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if (Psr & FDCAN_PSR_EP) {
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irq_reason = MP_OBJ_NEW_SMALL_INT(4);
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// mp_printf(MICROPY_ERROR_PRINTER, "clear passive %08x\n", (can->IR & FDCAN_ERROR_STATUS_MASK));
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}
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}
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if (ErrorStatusITs & FDCAN_FLAG_BUS_OFF) {
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__HAL_FDCAN_CLEAR_FLAG(&self->can, FDCAN_FLAG_BUS_OFF);
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if (Psr & FDCAN_PSR_BO) {
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irq_reason = MP_OBJ_NEW_SMALL_INT(5);
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// mp_printf(MICROPY_ERROR_PRINTER, "bus off %08x\n", (can->IR & FDCAN_ERROR_STATUS_MASK));
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}
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}
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pyb_can_handle_callback(self, fifo_id, callback, irq_reason);
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// mp_printf(MICROPY_ERROR_PRINTER, "Ints: %08x, %08x, %08x\n", RxFifo0ITs, RxFifo1ITs, ErrorStatusITs);
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}
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#if defined(MICROPY_HW_CAN1_TX)
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@ -64,7 +64,7 @@ class Lexer:
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(
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"#define typedef",
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re.compile(
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r"#define +(?P<id>[A-Z0-9_]+(ext)?) +\(\([A-Za-z0-9_]+_TypeDef \*\) (?P<id2>[A-Za-z0-9_]+)\)($| +/\*)"
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r"#define +(?P<id>[A-Z0-9_]+(ext)?) +\(\([A-Za-z0-9_]+_(Global)?TypeDef \*\) (?P<id2>[A-Za-z0-9_]+)\)($| +/\*)"
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),
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),
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("typedef struct", re.compile(r"typedef struct$")),
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@ -281,6 +281,7 @@ def main():
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#'CAN_FIFOMailBox',
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#'CAN_FilterRegister',
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#'CAN',
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"FDCAN",
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"CRC",
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"DAC",
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"DBGMCU",
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@ -47,8 +47,14 @@
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#define CAN_FIFO1 FDCAN_RX_FIFO1
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#define CAN_FILTER_FIFO0 (0)
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// Default timings; 125Kbps assuming 48MHz clock
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// Default timings; 125Kbps
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#if defined(STM32G4)
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// assuming 24MHz clock
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#define CAN_DEFAULT_PRESCALER (16)
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#else
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// assuming 48MHz clock
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#define CAN_DEFAULT_PRESCALER (32)
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#endif
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#define CAN_DEFAULT_SJW (1)
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#define CAN_DEFAULT_BS1 (8)
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#define CAN_DEFAULT_BS2 (3)
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@ -60,8 +66,10 @@
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#define CAN1_RX0_IRQn FDCAN1_IT0_IRQn
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#define CAN1_RX1_IRQn FDCAN1_IT1_IRQn
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#if defined(CAN2)
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#define CAN2_RX0_IRQn FDCAN2_IT0_IRQn
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#define CAN2_RX1_IRQn FDCAN2_IT1_IRQn
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#endif
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#define CAN_IT_FIFO0_FULL FDCAN_IT_RX_FIFO0_FULL
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#define CAN_IT_FIFO1_FULL FDCAN_IT_RX_FIFO1_FULL
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@ -326,6 +334,9 @@ STATIC mp_obj_t pyb_can_restart(mp_obj_t self_in) {
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can->CCCR |= FDCAN_CCCR_INIT;
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while ((can->CCCR & FDCAN_CCCR_INIT) == 0) {
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}
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can->CCCR |= FDCAN_CCCR_CCE;
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while ((can->CCCR & FDCAN_CCCR_CCE) == 0) {
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}
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can->CCCR &= ~FDCAN_CCCR_INIT;
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while ((can->CCCR & FDCAN_CCCR_INIT)) {
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}
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@ -348,11 +359,12 @@ STATIC mp_obj_t pyb_can_state(mp_obj_t self_in) {
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if (self->is_enabled) {
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CAN_TypeDef *can = self->can.Instance;
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#if MICROPY_HW_ENABLE_FDCAN
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if (can->PSR & FDCAN_PSR_BO) {
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uint32_t psr = can->PSR;
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if (psr & FDCAN_PSR_BO) {
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state = CAN_STATE_BUS_OFF;
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} else if (can->PSR & FDCAN_PSR_EP) {
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} else if (psr & FDCAN_PSR_EP) {
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state = CAN_STATE_ERROR_PASSIVE;
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} else if (can->PSR & FDCAN_PSR_EW) {
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} else if (psr & FDCAN_PSR_EW) {
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state = CAN_STATE_ERROR_WARNING;
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} else {
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state = CAN_STATE_ERROR_ACTIVE;
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@ -375,10 +387,6 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_can_state_obj, pyb_can_state);
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// Get info about error states and TX/RX buffers
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STATIC mp_obj_t pyb_can_info(size_t n_args, const mp_obj_t *args) {
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#if MICROPY_HW_ENABLE_FDCAN
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// TODO implement for FDCAN
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return mp_const_none;
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#else
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pyb_can_obj_t *self = MP_OBJ_TO_PTR(args[0]);
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mp_obj_list_t *list;
|
||||
if (n_args == 1) {
|
||||
|
|
@ -392,6 +400,20 @@ STATIC mp_obj_t pyb_can_info(size_t n_args, const mp_obj_t *args) {
|
|||
mp_raise_ValueError(NULL);
|
||||
}
|
||||
}
|
||||
|
||||
#if MICROPY_HW_ENABLE_FDCAN
|
||||
FDCAN_GlobalTypeDef *can = self->can.Instance;
|
||||
uint32_t esr = can->ECR;
|
||||
list->items[0] = MP_OBJ_NEW_SMALL_INT((esr & FDCAN_ECR_TEC_Msk) >> FDCAN_ECR_TEC_Pos);
|
||||
list->items[1] = MP_OBJ_NEW_SMALL_INT((esr & FDCAN_ECR_REC_Msk) >> FDCAN_ECR_REC_Pos);
|
||||
list->items[2] = MP_OBJ_NEW_SMALL_INT(self->num_error_warning);
|
||||
list->items[3] = MP_OBJ_NEW_SMALL_INT(self->num_error_passive);
|
||||
list->items[4] = MP_OBJ_NEW_SMALL_INT(self->num_bus_off);
|
||||
uint32_t TXEFS = can->TXEFS;
|
||||
list->items[5] = MP_OBJ_NEW_SMALL_INT(TXEFS & 0x7);
|
||||
list->items[6] = MP_OBJ_NEW_SMALL_INT((can->RXF0S & FDCAN_RXF0S_F0FL_Msk) >> FDCAN_RXF0S_F0FL_Pos);
|
||||
list->items[7] = MP_OBJ_NEW_SMALL_INT((can->RXF1S & FDCAN_RXF1S_F1FL_Msk) >> FDCAN_RXF1S_F1FL_Pos);
|
||||
#else
|
||||
CAN_TypeDef *can = self->can.Instance;
|
||||
uint32_t esr = can->ESR;
|
||||
list->items[0] = MP_OBJ_NEW_SMALL_INT(esr >> CAN_ESR_TEC_Pos & 0xff);
|
||||
|
|
@ -403,8 +425,9 @@ STATIC mp_obj_t pyb_can_info(size_t n_args, const mp_obj_t *args) {
|
|||
list->items[5] = MP_OBJ_NEW_SMALL_INT(n_tx_pending);
|
||||
list->items[6] = MP_OBJ_NEW_SMALL_INT(can->RF0R >> CAN_RF0R_FMP0_Pos & 3);
|
||||
list->items[7] = MP_OBJ_NEW_SMALL_INT(can->RF1R >> CAN_RF1R_FMP1_Pos & 3);
|
||||
return MP_OBJ_FROM_PTR(list);
|
||||
#endif
|
||||
|
||||
return MP_OBJ_FROM_PTR(list);
|
||||
}
|
||||
STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_can_info_obj, 1, 2, pyb_can_info);
|
||||
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue