kopia lustrzana https://github.com/micropython/micropython
492 wiersze
15 KiB
C
492 wiersze
15 KiB
C
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//*****************************************************************************
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//
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// wdt.c
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//
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// Driver for the Watchdog Timer Module.
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup WDT_Watchdog_Timer_api
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_ints.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_types.h"
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#include "inc/hw_wdt.h"
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#include "debug.h"
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#include "interrupt.h"
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#include "wdt.h"
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//*****************************************************************************
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//
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//! Determines if the watchdog timer is enabled.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! This will check to see if the watchdog timer is enabled.
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//!
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//! \return Returns \b true if the watchdog timer is enabled, and \b false
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//! if it is not.
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//
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//*****************************************************************************
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tBoolean
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WatchdogRunning(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WDT_BASE));
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//
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// See if the watchdog timer module is enabled, and return.
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//
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return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);
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}
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//*****************************************************************************
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//
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//! Enables the watchdog timer.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! This will enable the watchdog timer counter and interrupt.
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//!
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//! \note This function will have no effect if the watchdog timer has
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//! been locked.
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//!
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//! \sa WatchdogLock(), WatchdogUnlock()
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WDT_BASE));
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//
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// Enable the watchdog timer module.
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//
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HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
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}
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//*****************************************************************************
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//
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//! Enables the watchdog timer lock mechanism.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! Locks out write access to the watchdog timer configuration registers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogLock(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WDT_BASE));
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//
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// Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
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// register causes the lock to go into effect.
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//
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HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;
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}
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//*****************************************************************************
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//
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//! Disables the watchdog timer lock mechanism.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! Enables write access to the watchdog timer configuration registers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogUnlock(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WDT_BASE));
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//
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// Unlock watchdog register writes.
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//
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HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
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}
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//*****************************************************************************
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//
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//! Gets the state of the watchdog timer lock mechanism.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! Returns the lock state of the watchdog timer registers.
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//!
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//! \return Returns \b true if the watchdog timer registers are locked, and
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//! \b false if they are not locked.
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//
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//*****************************************************************************
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tBoolean
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WatchdogLockState(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WDT_BASE));
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//
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// Get the lock state.
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//
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return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
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}
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//*****************************************************************************
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//
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//! Sets the watchdog timer reload value.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//! \param ulLoadVal is the load value for the watchdog timer.
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//!
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//! This function sets the value to load into the watchdog timer when the count
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//! reaches zero for the first time; if the watchdog timer is running when this
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//! function is called, then the value will be immediately loaded into the
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//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an
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//! interrupt is immediately generated.
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//!
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//! \note This function will have no effect if the watchdog timer has
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//! been locked.
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//!
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//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WDT_BASE));
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//
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// Set the load register.
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//
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HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;
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}
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//*****************************************************************************
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//
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//! Gets the watchdog timer reload value.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! This function gets the value that is loaded into the watchdog timer when
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//! the count reaches zero for the first time.
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//!
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//! \sa WatchdogReloadSet()
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//!
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//! \return None.
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//
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//*****************************************************************************
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unsigned long
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WatchdogReloadGet(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WDT_BASE));
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//
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// Get the load register.
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//
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return(HWREG(ulBase + WDT_O_LOAD));
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}
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//*****************************************************************************
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//
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//! Gets the current watchdog timer value.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! This function reads the current value of the watchdog timer.
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//!
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//! \return Returns the current value of the watchdog timer.
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//
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//*****************************************************************************
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unsigned long
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WatchdogValueGet(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WDT_BASE));
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//
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// Get the current watchdog timer register value.
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//
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return(HWREG(ulBase + WDT_O_VALUE));
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}
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//*****************************************************************************
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//
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//! Registers an interrupt handler for watchdog timer interrupt.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//! \param pfnHandler is a pointer to the function to be called when the
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//! watchdog timer interrupt occurs.
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//!
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//! This function does the actual registering of the interrupt handler. This
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//! will enable the global interrupt in the interrupt controller; the watchdog
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//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt
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//! handler's responsibility to clear the interrupt source via
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//! WatchdogIntClear().
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \note This function will only register the standard watchdog interrupt
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//! handler. To register the NMI watchdog handler, use IntRegister()
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//! to register the handler for the \b FAULT_NMI interrupt.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WDT_BASE));
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//
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// Register the interrupt handler and
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// Enable the watchdog timer interrupt.
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//
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IntRegister(INT_WDT, pfnHandler);
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IntEnable(INT_WDT);
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}
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//*****************************************************************************
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//
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//! Unregisters an interrupt handler for the watchdog timer interrupt.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! This function does the actual unregistering of the interrupt handler. This
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//! function will clear the handler to be called when a watchdog timer
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//! interrupt occurs. This will also mask off the interrupt in the interrupt
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//! controller so that the interrupt handler no longer is called.
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \note This function will only unregister the standard watchdog interrupt
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//! handler. To unregister the NMI watchdog handler, use IntUnregister()
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//! to unregister the handler for the \b FAULT_NMI interrupt.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogIntUnregister(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WDT_BASE));
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//
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// Disable the interrupt
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IntDisable(INT_WDT);
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//
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// Unregister the interrupt handler.
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//
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IntUnregister(INT_WDT);
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}
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//*****************************************************************************
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//
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//! Gets the current watchdog timer interrupt status.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//! \param bMasked is \b false if the raw interrupt status is required and
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//! \b true if the masked interrupt status is required.
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//!
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//! This returns the interrupt status for the watchdog timer module. Either
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//! the raw interrupt status or the status of interrupt that is allowed to
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//! reflect to the processor can be returned.
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//!
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//! \return Returns the current interrupt status, where a 1 indicates that the
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//! watchdog interrupt is active, and a 0 indicates that it is not active.
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//
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//*****************************************************************************
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unsigned long
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WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WDT_BASE));
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//
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// Return either the interrupt status or the raw interrupt status as
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// requested.
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//
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if(bMasked)
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{
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return(HWREG(ulBase + WDT_O_MIS));
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}
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else
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{
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return(HWREG(ulBase + WDT_O_RIS));
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}
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}
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//*****************************************************************************
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//
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//! Clears the watchdog timer interrupt.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! The watchdog timer interrupt source is cleared, so that it no longer
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//! asserts.
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//!
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//! \note Because there is a write buffer in the Cortex-M3 processor, it may
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//! take several clock cycles before the interrupt source is actually cleared.
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//! Therefore, it is recommended that the interrupt source be cleared early in
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//! the interrupt handler (as opposed to the very last action) to avoid
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//! returning from the interrupt handler before the interrupt source is
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//! actually cleared. Failure to do so may result in the interrupt handler
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//! being immediately reentered (because the interrupt controller still sees
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//! the interrupt source asserted).
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogIntClear(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
|
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ASSERT((ulBase == WDT_BASE));
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|
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//
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// Clear the interrupt source.
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//
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HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
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}
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|
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||
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//*****************************************************************************
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||
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//
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||
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//! Enables stalling of the watchdog timer during debug events.
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||
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//!
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||
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//! \param ulBase is the base address of the watchdog timer module.
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||
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//!
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||
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//! This function allows the watchdog timer to stop counting when the processor
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//! is stopped by the debugger. By doing so, the watchdog is prevented from
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//! expiring (typically almost immediately from a human time perspective) and
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//! resetting the system (if reset is enabled). The watchdog will instead
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||
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//! expired after the appropriate number of processor cycles have been executed
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||
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//! while debugging (or at the appropriate time after the processor has been
|
||
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//! restarted).
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||
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//!
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||
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//! \return None.
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||
|
//
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||
|
//*****************************************************************************
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||
|
void
|
||
|
WatchdogStallEnable(unsigned long ulBase)
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||
|
{
|
||
|
//
|
||
|
// Check the arguments.
|
||
|
//
|
||
|
ASSERT((ulBase == WDT_BASE));
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||
|
|
||
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//
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||
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// Enable timer stalling.
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||
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//
|
||
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HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;
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||
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}
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||
|
|
||
|
//*****************************************************************************
|
||
|
//
|
||
|
//! Disables stalling of the watchdog timer during debug events.
|
||
|
//!
|
||
|
//! \param ulBase is the base address of the watchdog timer module.
|
||
|
//!
|
||
|
//! This function disables the debug mode stall of the watchdog timer. By
|
||
|
//! doing so, the watchdog timer continues to count regardless of the processor
|
||
|
//! debug state.
|
||
|
//!
|
||
|
//! \return None.
|
||
|
//
|
||
|
//*****************************************************************************
|
||
|
void
|
||
|
WatchdogStallDisable(unsigned long ulBase)
|
||
|
{
|
||
|
//
|
||
|
// Check the arguments.
|
||
|
//
|
||
|
ASSERT((ulBase == WDT_BASE));
|
||
|
|
||
|
//
|
||
|
// Disable timer stalling.
|
||
|
//
|
||
|
HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);
|
||
|
}
|
||
|
|
||
|
//*****************************************************************************
|
||
|
//
|
||
|
// Close the Doxygen group.
|
||
|
//! @}
|
||
|
//
|
||
|
//*****************************************************************************
|