kopia lustrzana https://github.com/micropython/micropython
418 wiersze
23 KiB
C
418 wiersze
23 KiB
C
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//*****************************************************************************
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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#ifndef __HW_UART_H__
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#define __HW_UART_H__
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//*****************************************************************************
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//
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// The following are defines for the UART register offsets.
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//
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//*****************************************************************************
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#define UART_O_DR 0x00000000
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#define UART_O_RSR 0x00000004
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#define UART_O_ECR 0x00000004
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#define UART_O_FR 0x00000018
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#define UART_O_ILPR 0x00000020
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#define UART_O_IBRD 0x00000024
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#define UART_O_FBRD 0x00000028
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#define UART_O_LCRH 0x0000002C
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#define UART_O_CTL 0x00000030
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#define UART_O_IFLS 0x00000034
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#define UART_O_IM 0x00000038
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#define UART_O_RIS 0x0000003C
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#define UART_O_MIS 0x00000040
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#define UART_O_ICR 0x00000044
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#define UART_O_DMACTL 0x00000048
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#define UART_O_LCTL 0x00000090
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#define UART_O_LSS 0x00000094
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#define UART_O_LTIM 0x00000098
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#define UART_O_9BITADDR 0x000000A4
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#define UART_O_9BITAMASK 0x000000A8
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#define UART_O_PP 0x00000FC0
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#define UART_O_CC 0x00000FC8
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_DR register.
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//
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//******************************************************************************
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#define UART_DR_OE 0x00000800 // UART Overrun Error
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#define UART_DR_BE 0x00000400 // UART Break Error
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#define UART_DR_PE 0x00000200 // UART Parity Error
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#define UART_DR_FE 0x00000100 // UART Framing Error
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#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
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#define UART_DR_DATA_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_RSR register.
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//
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//******************************************************************************
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#define UART_RSR_OE 0x00000008 // UART Overrun Error
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#define UART_RSR_BE 0x00000004 // UART Break Error
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#define UART_RSR_PE 0x00000002 // UART Parity Error
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#define UART_RSR_FE 0x00000001 // UART Framing Error
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_ECR register.
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//
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//******************************************************************************
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#define UART_ECR_DATA_M 0x000000FF // Error Clear
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#define UART_ECR_DATA_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_FR register.
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//
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//******************************************************************************
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#define UART_FR_RI 0x00000100 // Ring Indicator
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#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
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#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
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#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
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#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
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#define UART_FR_BUSY 0x00000008 // UART Busy
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#define UART_FR_DCD 0x00000004 // Data Carrier Detect
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#define UART_FR_DSR 0x00000002 // Data Set Ready
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#define UART_FR_CTS 0x00000001 // Clear To Send
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_ILPR register.
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//
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//******************************************************************************
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#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
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#define UART_ILPR_ILPDVSR_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_IBRD register.
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//
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//******************************************************************************
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#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
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#define UART_IBRD_DIVINT_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_FBRD register.
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//
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//******************************************************************************
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#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
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#define UART_FBRD_DIVFRAC_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_LCRH register.
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//
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//******************************************************************************
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#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
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#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 0x00000000 :
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// UART_LCRH_WLEN_5 : 5 bits
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// (default) 0x00000020 :
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// UART_LCRH_WLEN_6 : 6 bits
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// 0x00000040 : UART_LCRH_WLEN_7 : 7
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// bits 0x00000060 :
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// UART_LCRH_WLEN_8 : 8 bits
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#define UART_LCRH_WLEN_S 5
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#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
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#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
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#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
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#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
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#define UART_LCRH_BRK 0x00000001 // UART Send Break
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#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
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#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
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#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
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#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
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#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_CTL register.
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//
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//******************************************************************************
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#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
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#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
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#define UART_CTL_RI 0x00002000 // Ring Indicator
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#define UART_CTL_DCD 0x00001000 // Data Carrier Detect
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#define UART_CTL_RTS 0x00000800 // Request to Send
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#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
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#define UART_CTL_RXE 0x00000200 // UART Receive Enable
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#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
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#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
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#define UART_CTL_LIN 0x00000040 // LIN Mode Enable
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#define UART_CTL_HSE 0x00000020 // High-Speed Enable
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#define UART_CTL_EOT 0x00000010 // End of Transmission
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#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
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#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
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#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
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#define UART_CTL_UARTEN 0x00000001 // UART Enable
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_IFLS register.
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//
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//******************************************************************************
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#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
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// Level Select
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#define UART_IFLS_RX_S 3
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#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
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// Level Select
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#define UART_IFLS_TX_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_IM register.
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//
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//******************************************************************************
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#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask
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#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask
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#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask
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#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
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#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
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// Mask
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#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
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#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt
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// Mask
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#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
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// Mask
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#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
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#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
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#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
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// Mask
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#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
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// Mask
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#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
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#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
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#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
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// Interrupt Mask
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#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
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// Interrupt Mask
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#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
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// Interrupt Mask
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#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
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// Interrupt Mask
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_RIS register.
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//
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//******************************************************************************
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#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt
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// Status
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#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status
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#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
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// Status
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#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
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// Status
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#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
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// Interrupt Status
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#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
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#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw
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// Interrupt Status
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#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
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// Status
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#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
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// Status
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#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
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// Status
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#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
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// Status
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#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
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// Interrupt Status
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#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
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// Status
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#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
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// Status
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#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
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// Interrupt Status
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#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
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// Raw Interrupt Status
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#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
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// Interrupt Status
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#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
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// Interrupt Status
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_MIS register.
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//
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//******************************************************************************
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#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt
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// Status
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#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt
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// Status
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#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
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// Status
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#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
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// Status
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#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
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// Interrupt Status
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#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
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// Status
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#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked
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// Interrupt Status
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#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
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// Interrupt Status
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#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
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// Interrupt Status
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#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
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// Interrupt Status
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#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
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// Interrupt Status
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#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
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// Interrupt Status
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#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
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// Status
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#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
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// Status
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#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
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// Interrupt Status
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#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
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// Masked Interrupt Status
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#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
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// Interrupt Status
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#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
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// Interrupt Status
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_ICR register.
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//
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//******************************************************************************
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#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear
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#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear
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#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
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#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
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#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
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// Clear
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#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
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#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt
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// Clear
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#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
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#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
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#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
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#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
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#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
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#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
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#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
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#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
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// Interrupt Clear
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#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
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// Interrupt Clear
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#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
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// Interrupt Clear
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#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
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// Interrupt Clear
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_DMACTL register.
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//
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//******************************************************************************
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#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
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#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
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#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UART_O_LCTL register.
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//
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//******************************************************************************
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#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length 0x00000000 :
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// UART_LCTL_BLEN_13T : Sync break
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// length is 13T bits (default)
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// 0x00000010 : UART_LCTL_BLEN_14T :
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// Sync break length is 14T bits
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// 0x00000020 : UART_LCTL_BLEN_15T :
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||
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// Sync break length is 15T bits
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||
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// 0x00000030 : UART_LCTL_BLEN_16T :
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||
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// Sync break length is 16T bits
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#define UART_LCTL_BLEN_S 4
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|
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#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable
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||
|
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//******************************************************************************
|
||
|
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//
|
||
|
|
// The following are defines for the bit fields in the UART_O_LSS register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
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#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot
|
||
|
|
#define UART_LSS_TSS_S 0
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the UART_O_LTIM register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
|
||
|
|
#define UART_LTIM_TIMER_S 0
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// UART_O_9BITADDR register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define UART_9BITADDR_9BITEN \
|
||
|
|
0x00008000 // Enable 9-Bit Mode
|
||
|
|
|
||
|
|
#define UART_9BITADDR_ADDR_M \
|
||
|
|
0x000000FF // Self Address for 9-Bit Mode
|
||
|
|
|
||
|
|
#define UART_9BITADDR_ADDR_S 0
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// UART_O_9BITAMASK register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define UART_9BITAMASK_RANGE_M \
|
||
|
|
0x0000FF00 // Self Address Range for 9-Bit
|
||
|
|
// Mode
|
||
|
|
|
||
|
|
#define UART_9BITAMASK_RANGE_S 8
|
||
|
|
#define UART_9BITAMASK_MASK_M \
|
||
|
|
0x000000FF // Self Address Mask for 9-Bit Mode
|
||
|
|
|
||
|
|
#define UART_9BITAMASK_MASK_S 0
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the UART_O_PP register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define UART_PP_MSE 0x00000008 // Modem Support Extended
|
||
|
|
#define UART_PP_MS 0x00000004 // Modem Support
|
||
|
|
#define UART_PP_NB 0x00000002 // 9-Bit Support
|
||
|
|
#define UART_PP_SC 0x00000001 // Smart Card Support
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the UART_O_CC register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
|
||
|
|
// 0x00000005 : UART_CC_CS_PIOSC :
|
||
|
|
// PIOSC 0x00000000 :
|
||
|
|
// UART_CC_CS_SYSCLK : The system
|
||
|
|
// clock (default)
|
||
|
|
#define UART_CC_CS_S 0
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#endif // __HW_UART_H__
|