kopia lustrzana https://github.com/micropython/micropython
693 wiersze
20 KiB
C
693 wiersze
20 KiB
C
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//*****************************************************************************
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//
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// adc.c
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//
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// Driver for the ADC module.
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup ADC_Analog_to_Digital_Converter_api
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_types.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_ints.h"
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#include "inc/hw_adc.h"
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#include "inc/hw_apps_config.h"
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#include "interrupt.h"
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#include "adc.h"
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//*****************************************************************************
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//
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//! Enables the ADC
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//!
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//! \param ulBase is the base address of the ADC
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//!
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//! This function sets the ADC global enable
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//!
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//! \return None.
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//
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//*****************************************************************************
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void ADCEnable(unsigned long ulBase)
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{
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//
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// Set the global enable bit in the control register.
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//
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HWREG(ulBase + ADC_O_ADC_CTRL) |= 0x1;
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}
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//*****************************************************************************
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//
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//! Disable the ADC
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//!
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//! \param ulBase is the base address of the ADC
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//!
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//! This function clears the ADC global enable
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//!
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//! \return None.
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//
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//*****************************************************************************
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void ADCDisable(unsigned long ulBase)
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{
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//
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// Clear the global enable bit in the control register.
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//
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HWREG(ulBase + ADC_O_ADC_CTRL) &= ~0x1 ;
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}
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//*****************************************************************************
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//
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//! Enables specified ADC channel
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//!
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//! \param ulBase is the base address of the ADC
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//! \param ulChannel is one of the valid ADC channels
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//!
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//! This function enables specified ADC channel and configures the
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//! pin as analog pin.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void ADCChannelEnable(unsigned long ulBase, unsigned long ulChannel)
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{
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unsigned long ulCh;
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ulCh = (ulChannel == ADC_CH_0)? 0x02 :
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(ulChannel == ADC_CH_1)? 0x04 :
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(ulChannel == ADC_CH_2)? 0x08 : 0x10;
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HWREG(ulBase + ADC_O_ADC_CH_ENABLE) |= ulCh;
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}
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//*****************************************************************************
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//
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//! Disables specified ADC channel
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//!
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//! \param ulBase is the base address of the ADC
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//! \param ulChannel is one of the valid ADC channelsber
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//!
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//! This function disables specified ADC channel.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void ADCChannelDisable(unsigned long ulBase, unsigned long ulChannel)
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{
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unsigned long ulCh;
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ulCh = (ulChannel == ADC_CH_0)? 0x02 :
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(ulChannel == ADC_CH_1)? 0x04 :
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(ulChannel == ADC_CH_2)? 0x08 : 0x10;
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HWREG(ulBase + ADC_O_ADC_CH_ENABLE) &= ~ulCh;
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}
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//*****************************************************************************
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//
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//! Enables and registers ADC interrupt handler for specified channel
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//!
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//! \param ulBase is the base address of the ADC
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//! \param ulChannel is one of the valid ADC channels
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//! \param pfnHandler is a pointer to the function to be called when the
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//! ADC channel interrupt occurs.
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//!
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//! This function enables and registers ADC interrupt handler for specified
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//! channel. Individual interrupt for each channel should be enabled using
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//! \sa ADCIntEnable(). It is the interrupt handler's responsibility to clear
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//! the interrupt source.
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//!
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//! The parameter \e ulChannel should be one of the following
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//!
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//! - \b ADC_CH_0 for channel 0
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//! - \b ADC_CH_1 for channel 1
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//! - \b ADC_CH_2 for channel 2
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//! - \b ADC_CH_3 for channel 3
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//!
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//! \return None.
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//
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//*****************************************************************************
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void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel,
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void (*pfnHandler)(void))
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{
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unsigned long ulIntNo;
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//
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// Get the interrupt number associted with the specified channel
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//
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ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 :
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(ulChannel == ADC_CH_1)? INT_ADCCH1 :
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(ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3;
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//
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// Register the interrupt handler
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//
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IntRegister(ulIntNo,pfnHandler);
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//
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// Enable ADC interrupt
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//
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IntEnable(ulIntNo);
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}
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//*****************************************************************************
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//
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//! Disables and unregisters ADC interrupt handler for specified channel
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//!
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//! \param ulBase is the base address of the ADC
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//! \param ulChannel is one of the valid ADC channels
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//!
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//! This function disables and unregisters ADC interrupt handler for specified
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//! channel. This function also masks off the interrupt in the interrupt
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//! controller so that the interrupt handler no longer is called.
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//!
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//! The parameter \e ulChannel should be one of the following
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//!
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//! - \b ADC_CH_0 for channel 0
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//! - \b ADC_CH_1 for channel 1
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//! - \b ADC_CH_2 for channel 2
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//! - \b ADC_CH_3 for channel 3
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//!
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//! \return None.
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//
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//*****************************************************************************
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void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel)
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{
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unsigned long ulIntNo;
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//
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// Get the interrupt number associted with the specified channel
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//
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ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 :
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(ulChannel == ADC_CH_1)? INT_ADCCH1 :
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(ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3;
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//
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// Disable ADC interrupt
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//
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IntDisable(ulIntNo);
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//
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// Unregister the interrupt handler
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//
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IntUnregister(ulIntNo);
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}
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//*****************************************************************************
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//
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//! Enables individual interrupt sources for specified channel
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//!
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//!
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//! \param ulBase is the base address of the ADC
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//! \param ulChannel is one of the valid ADC channels
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//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
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//!
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//! This function enables the indicated ADC interrupt sources. Only the
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//! sources that are enabled can be reflected to the processor interrupt;
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//! disabled sources have no effect on the processor.
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//!
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//! The parameter \e ulChannel should be one of the following
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//!
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//! - \b ADC_CH_0 for channel 0
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//! - \b ADC_CH_1 for channel 1
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//! - \b ADC_CH_2 for channel 2
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//! - \b ADC_CH_3 for channel 3
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//!
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//! The \e ulIntFlags parameter is the logical OR of any of the following:
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//! - \b ADC_DMA_DONE for DMA done
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//! - \b ADC_FIFO_OVERFLOW for FIFO over flow
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//! - \b ADC_FIFO_UNDERFLOW for FIFO under flow
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//! - \b ADC_FIFO_EMPTY for FIFO empty
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//! - \b ADC_FIFO_FULL for FIFO full
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//!
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//! \return None.
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//
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//*****************************************************************************
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void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel,
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unsigned long ulIntFlags)
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{
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unsigned long ulOffset;
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unsigned long ulDmaMsk;
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//
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// Enable DMA Done interrupt
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//
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if(ulIntFlags & ADC_DMA_DONE)
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{
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ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
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(ulChannel == ADC_CH_1)?0x00002000:
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(ulChannel == ADC_CH_2)?0x00004000:0x00008000;
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HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
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}
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ulIntFlags = ulIntFlags & 0x0F;
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//
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// Get the interrupt enable register offset for specified channel
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//
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ulOffset = ADC_O_adc_ch0_irq_en + ulChannel;
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//
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// Unmask the specified interrupts
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//
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HWREG(ulBase + ulOffset) |= (ulIntFlags & 0xf);
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}
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//*****************************************************************************
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//
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//! Disables individual interrupt sources for specified channel
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//!
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//!
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//! \param ulBase is the base address of the ADC.
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//! \param ulChannel is one of the valid ADC channels
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//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
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//!
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//! This function disables the indicated ADC interrupt sources. Only the
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//! sources that are enabled can be reflected to the processor interrupt;
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//! disabled sources have no effect on the processor.
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//!
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//! The parameters\e ulIntFlags and \e ulChannel should be as explained in
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//! ADCIntEnable().
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//!
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//! \return None.
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//
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//*****************************************************************************
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void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel,
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unsigned long ulIntFlags)
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{
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unsigned long ulOffset;
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unsigned long ulDmaMsk;
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//
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// Disable DMA Done interrupt
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//
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if(ulIntFlags & ADC_DMA_DONE)
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{
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ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
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(ulChannel == ADC_CH_1)?0x00002000:
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(ulChannel == ADC_CH_2)?0x00004000:0x00008000;
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HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
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}
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//
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// Get the interrupt enable register offset for specified channel
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//
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ulOffset = ADC_O_adc_ch0_irq_en + ulChannel;
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//
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// Unmask the specified interrupts
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//
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HWREG(ulBase + ulOffset) &= ~ulIntFlags;
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}
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//*****************************************************************************
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//
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//! Gets the current channel interrupt status
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//!
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//! \param ulBase is the base address of the ADC
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//! \param ulChannel is one of the valid ADC channels
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//!
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//! This function returns the interrupt status of the specified ADC channel.
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//!
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//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable().
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//!
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//! \return Return the ADC channel interrupt status, enumerated as a bit
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//! field of values described in ADCIntEnable()
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//
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//*****************************************************************************
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unsigned long ADCIntStatus(unsigned long ulBase, unsigned long ulChannel)
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{
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unsigned long ulOffset;
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unsigned long ulDmaMsk;
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unsigned long ulIntStatus;
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//
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// Get DMA Done interrupt status
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//
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ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
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(ulChannel == ADC_CH_1)?0x00002000:
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(ulChannel == ADC_CH_2)?0x00004000:0x00008000;
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ulIntStatus = HWREG(APPS_CONFIG_BASE +
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APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED)& ulDmaMsk;
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//
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// Get the interrupt enable register offset for specified channel
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//
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ulOffset = ADC_O_adc_ch0_irq_status + ulChannel;
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//
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// Read ADC interrupt status
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//
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ulIntStatus |= HWREG(ulBase + ulOffset) & 0xf;
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//
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// Return the current interrupt status
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//
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return(ulIntStatus);
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}
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//*****************************************************************************
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//
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//! Clears the current channel interrupt sources
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//!
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//! \param ulBase is the base address of the ADC
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//! \param ulChannel is one of the valid ADC channels
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//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
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//!
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//! This function clears individual interrupt source for the specified
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//! ADC channel.
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//!
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//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable().
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//!
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//! \return None.
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//
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//*****************************************************************************
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void ADCIntClear(unsigned long ulBase, unsigned long ulChannel,
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unsigned long ulIntFlags)
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{
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unsigned long ulOffset;
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unsigned long ulDmaMsk;
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|
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//
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// Clear DMA Done interrupt
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//
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if(ulIntFlags & ADC_DMA_DONE)
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{
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ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
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(ulChannel == ADC_CH_1)?0x00002000:
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(ulChannel == ADC_CH_2)?0x00004000:0x00008000;
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HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
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}
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//
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// Get the interrupt enable register offset for specified channel
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//
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ulOffset = ADC_O_adc_ch0_irq_status + ulChannel;
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//
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// Clear the specified interrupts
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//
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HWREG(ulBase + ulOffset) = (ulIntFlags & ~(ADC_DMA_DONE));
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}
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//*****************************************************************************
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||
|
//
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||
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//! Enables the ADC DMA operation for specified channel
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||
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//!
|
||
|
//! \param ulBase is the base address of the ADC
|
||
|
//! \param ulChannel is one of the valid ADC channels
|
||
|
//!
|
||
|
//! This function enables the DMA operation for specified ADC channel
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||
|
//!
|
||
|
//! The parameter \e ulChannel should be one of the following
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||
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//!
|
||
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//! - \b ADC_CH_0 for channel 0
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||
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//! - \b ADC_CH_1 for channel 1
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||
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//! - \b ADC_CH_2 for channel 2
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||
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//! - \b ADC_CH_3 for channel 3
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||
|
//!
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||
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//! \return None.
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||
|
//
|
||
|
//*****************************************************************************
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||
|
void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel)
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||
|
{
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|
unsigned long ulBitMask;
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||
|
|
||
|
//
|
||
|
// Get the bit mask for enabling DMA for specified channel
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||
|
//
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||
|
ulBitMask = (ulChannel == ADC_CH_0)?0x01:
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||
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(ulChannel == ADC_CH_1)?0x04:
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||
|
(ulChannel == ADC_CH_2)?0x10:0x40;
|
||
|
|
||
|
//
|
||
|
// Enable DMA request for the specified channel
|
||
|
//
|
||
|
HWREG(ulBase + ADC_O_adc_dma_mode_en) |= ulBitMask;
|
||
|
}
|
||
|
|
||
|
//*****************************************************************************
|
||
|
//
|
||
|
//! Disables the ADC DMA operation for specified channel
|
||
|
//!
|
||
|
//! \param ulBase is the base address of the ADC
|
||
|
//! \param ulChannel is one of the valid ADC channels
|
||
|
//!
|
||
|
//! This function disables the DMA operation for specified ADC channel
|
||
|
//!
|
||
|
//! The parameter \e ulChannel should be one of the following
|
||
|
//!
|
||
|
//! - \b ADC_CH_0 for channel 0
|
||
|
//! - \b ADC_CH_1 for channel 1
|
||
|
//! - \b ADC_CH_2 for channel 2
|
||
|
//! - \b ADC_CH_3 for channel 3
|
||
|
//!
|
||
|
//! \return None.
|
||
|
//
|
||
|
//*****************************************************************************
|
||
|
void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel)
|
||
|
{
|
||
|
unsigned long ulBitMask;
|
||
|
|
||
|
//
|
||
|
// Get the bit mask for disabling DMA for specified channel
|
||
|
//
|
||
|
ulBitMask = (ulChannel == ADC_CH_0)?0x01:
|
||
|
(ulChannel == ADC_CH_1)?0x04:
|
||
|
(ulChannel == ADC_CH_2)?0x10:0x40;
|
||
|
|
||
|
//
|
||
|
// Disable DMA request for the specified channel
|
||
|
//
|
||
|
HWREG(ulBase + ADC_O_adc_dma_mode_en) &= ~ulBitMask;
|
||
|
}
|
||
|
|
||
|
//*****************************************************************************
|
||
|
//
|
||
|
//! Configures the ADC internal timer
|
||
|
//!
|
||
|
//! \param ulBase is the base address of the ADC
|
||
|
//! \param ulValue is wrap arround value of the timer
|
||
|
//!
|
||
|
//! This function Configures the ADC internal timer. The ADC timer is a 17 bit
|
||
|
//! used to timestamp the ADC data samples internally.
|
||
|
//! User can read the timestamp along with the sample from the FIFO register(s).
|
||
|
//! Each sample in the FIFO contains 14 bit actual data and 18 bit timestamp
|
||
|
//!
|
||
|
//! The parameter \e ulValue can take any value between 0 - 2^17
|
||
|
//!
|
||
|
//! \returns None.
|
||
|
//
|
||
|
//*****************************************************************************
|
||
|
void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue)
|
||
|
{
|
||
|
unsigned long ulReg;
|
||
|
|
||
|
//
|
||
|
// Read the currrent config
|
||
|
//
|
||
|
ulReg = HWREG(ulBase + ADC_O_adc_timer_configuration);
|
||
|
|
||
|
//
|
||
|
// Mask and set timer count field
|
||
|
//
|
||
|
ulReg = ((ulReg & ~0x1FFFF) | (ulValue & 0x1FFFF));
|
||
|
|
||
|
//
|
||
|
// Set the timer count value
|
||
|
//
|
||
|
HWREG(ulBase + ADC_O_adc_timer_configuration) = ulReg;
|
||
|
}
|
||
|
|
||
|
//*****************************************************************************
|
||
|
//
|
||
|
//! Resets ADC internal timer
|
||
|
//!
|
||
|
//! \param ulBase is the base address of the ADC
|
||
|
//!
|
||
|
//! This function resets 17-bit ADC internal timer
|
||
|
//!
|
||
|
//! \returns None.
|
||
|
//
|
||
|
//*****************************************************************************
|
||
|
void ADCTimerReset(unsigned long ulBase)
|
||
|
{
|
||
|
//
|
||
|
// Reset the timer
|
||
|
//
|
||
|
HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 24);
|
||
|
}
|
||
|
|
||
|
//*****************************************************************************
|
||
|
//
|
||
|
//! Enables ADC internal timer
|
||
|
//!
|
||
|
//! \param ulBase is the base address of the ADC
|
||
|
//!
|
||
|
//! This function enables 17-bit ADC internal timer
|
||
|
//!
|
||
|
//! \returns None.
|
||
|
//
|
||
|
//*****************************************************************************
|
||
|
void ADCTimerEnable(unsigned long ulBase)
|
||
|
{
|
||
|
//
|
||
|
// Enable the timer
|
||
|
//
|
||
|
HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 25);
|
||
|
}
|
||
|
|
||
|
//*****************************************************************************
|
||
|
//
|
||
|
//! Disables ADC internal timer
|
||
|
//!
|
||
|
//! \param ulBase is the base address of the ADC
|
||
|
//!
|
||
|
//! This function disables 17-bit ADC internal timer
|
||
|
//!
|
||
|
//! \returns None.
|
||
|
//
|
||
|
//*****************************************************************************
|
||
|
void ADCTimerDisable(unsigned long ulBase)
|
||
|
{
|
||
|
//
|
||
|
// Disable the timer
|
||
|
//
|
||
|
HWREG(ulBase + ADC_O_adc_timer_configuration) &= ~(1 << 25);
|
||
|
}
|
||
|
|
||
|
//*****************************************************************************
|
||
|
//
|
||
|
//! Gets the current value of ADC internal timer
|
||
|
//!
|
||
|
//! \param ulBase is the base address of the ADC
|
||
|
//!
|
||
|
//! This function the current value of 17-bit ADC internal timer
|
||
|
//!
|
||
|
//! \returns Return the current value of ADC internal timer.
|
||
|
//
|
||
|
//*****************************************************************************
|
||
|
unsigned long ADCTimerValueGet(unsigned long ulBase)
|
||
|
{
|
||
|
return(HWREG(ulBase + ADC_O_adc_timer_current_count));
|
||
|
}
|
||
|
|
||
|
//*****************************************************************************
|
||
|
//
|
||
|
//! Gets the current FIFO level for specified ADC channel
|
||
|
//!
|
||
|
//! \param ulBase is the base address of the ADC
|
||
|
//! \param ulChannel is one of the valid ADC channels.
|
||
|
//!
|
||
|
//! This function returns the current FIFO level for specified ADC channel.
|
||
|
//!
|
||
|
//! The parameter \e ulChannel should be one of the following
|
||
|
//!
|
||
|
//! - \b ADC_CH_0 for channel 0
|
||
|
//! - \b ADC_CH_1 for channel 1
|
||
|
//! - \b ADC_CH_2 for channel 2
|
||
|
//! - \b ADC_CH_3 for channel 3
|
||
|
//!
|
||
|
//! \returns Return the current FIFO level for specified channel
|
||
|
//
|
||
|
//*****************************************************************************
|
||
|
unsigned char ADCFIFOLvlGet(unsigned long ulBase, unsigned long ulChannel)
|
||
|
{
|
||
|
unsigned long ulOffset;
|
||
|
|
||
|
//
|
||
|
// Get the fifo level register offset for specified channel
|
||
|
//
|
||
|
ulOffset = ADC_O_adc_ch0_fifo_lvl + ulChannel;
|
||
|
|
||
|
//
|
||
|
// Return FIFO level
|
||
|
//
|
||
|
return(HWREG(ulBase + ulOffset) & 0x7);
|
||
|
}
|
||
|
|
||
|
//*****************************************************************************
|
||
|
//
|
||
|
//! Reads FIFO for specified ADC channel
|
||
|
//!
|
||
|
//! \param ulBase is the base address of the ADC
|
||
|
//! \param ulChannel is one of the valid ADC channels.
|
||
|
//!
|
||
|
//! This function returns one data sample from the channel fifo as specified by
|
||
|
//! \e ulChannel parameter.
|
||
|
//!
|
||
|
//! The parameter \e ulChannel should be one of the following
|
||
|
//!
|
||
|
//! - \b ADC_CH_0 for channel 0
|
||
|
//! - \b ADC_CH_1 for channel 1
|
||
|
//! - \b ADC_CH_2 for channel 2
|
||
|
//! - \b ADC_CH_3 for channel 3
|
||
|
//!
|
||
|
//! \returns Return one data sample from the channel fifo.
|
||
|
//
|
||
|
//*****************************************************************************
|
||
|
unsigned long ADCFIFORead(unsigned long ulBase, unsigned long ulChannel)
|
||
|
{
|
||
|
unsigned long ulOffset;
|
||
|
|
||
|
//
|
||
|
// Get the fifo register offset for specified channel
|
||
|
//
|
||
|
ulOffset = ADC_O_channel0FIFODATA + ulChannel;
|
||
|
|
||
|
//
|
||
|
// Return FIFO level
|
||
|
//
|
||
|
return(HWREG(ulBase + ulOffset));
|
||
|
}
|
||
|
|
||
|
|
||
|
//*****************************************************************************
|
||
|
//
|
||
|
// Close the Doxygen group.
|
||
|
//! @}
|
||
|
//
|
||
|
//*****************************************************************************
|