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micropython/ports/samd/samd_soc.h

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samd: Add new port to Microchip SAMDxx microcontrollers. Initially supporting SAMD21 and SAMD51.
2019-06-22 13:03:41 +00:00
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2019 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef MICROPY_INCLUDED_SAMD_SAMD_SOC_H
#define MICROPY_INCLUDED_SAMD_SAMD_SOC_H
#include <stdint.h>
#include "sam.h"
samd/clock_config: Set up the clock configuration. Clock settings: - GCLK0: 48 MHz (SAMD21) or 120 MHz(SAMD51). - GCLK1: 32768 Hz for driving the PLL. - GCLK2: 48 MHz for tzhe peripheral clock. - GCLK3: 1 MHz (SAMD21) or 8 MHz (SAMD51) for the µs ticks timer. - GCLK8: 1 kHz for WDT (SAMD21 only). If a 32 kHz crystal is present, it will be used as clock source. Otherwise the DFLL48M in open-loop mode is used. GCLK0 for SAM51 can be changed between 48 MHz and 200 MHz. The specified range is 96 MHz - 120 MHz.
2022-06-04 14:31:46 +00:00
#include "clock_config.h"
samd: Add new port to Microchip SAMDxx microcontrollers. Initially supporting SAMD21 and SAMD51.
2019-06-22 13:03:41 +00:00
void samd_init(void);
void samd_main(void);
void USB_Handler_wrapper(void);
void USB_0_Handler_wrapper(void);
void USB_1_Handler_wrapper(void);
void USB_2_Handler_wrapper(void);
void USB_3_Handler_wrapper(void);
samd/clock_config: Set up the clock configuration. Clock settings: - GCLK0: 48 MHz (SAMD21) or 120 MHz(SAMD51). - GCLK1: 32768 Hz for driving the PLL. - GCLK2: 48 MHz for tzhe peripheral clock. - GCLK3: 1 MHz (SAMD21) or 8 MHz (SAMD51) for the µs ticks timer. - GCLK8: 1 kHz for WDT (SAMD21 only). If a 32 kHz crystal is present, it will be used as clock source. Otherwise the DFLL48M in open-loop mode is used. GCLK0 for SAM51 can be changed between 48 MHz and 200 MHz. The specified range is 96 MHz - 120 MHz.
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void sercom_enable(Sercom *spi, int state);
samd/samd_isr: Change the way a Sercom ISR is registered and called. Code size diff: +12 Bytes BSS diff: -12 Bytes RAM usage: +16 Bytes Speed increase: a few clock cycles per call Style improvement: ++
2022-06-06 08:20:44 +00:00
void sercom_register_irq(int sercom_id, void (*sercom_irq_handler));
samd/clock_config: Set up the clock configuration. Clock settings: - GCLK0: 48 MHz (SAMD21) or 120 MHz(SAMD51). - GCLK1: 32768 Hz for driving the PLL. - GCLK2: 48 MHz for tzhe peripheral clock. - GCLK3: 1 MHz (SAMD21) or 8 MHz (SAMD51) for the µs ticks timer. - GCLK8: 1 kHz for WDT (SAMD21 only). If a 32 kHz crystal is present, it will be used as clock source. Otherwise the DFLL48M in open-loop mode is used. GCLK0 for SAM51 can be changed between 48 MHz and 200 MHz. The specified range is 96 MHz - 120 MHz.
2022-06-04 14:31:46 +00:00
#define SERCOM_IRQ_TYPE_UART (0)
#define SERCOM_IRQ_TYPE_SPI (1)
#define SERCOM_IRQ_TYPE_I2C (2)
samd: Add new port to Microchip SAMDxx microcontrollers. Initially supporting SAMD21 and SAMD51.
2019-06-22 13:03:41 +00:00
#endif // MICROPY_INCLUDED_SAMD_SAMD_SOC_H