kopia lustrzana https://github.com/peterhinch/micropython-samples
47 wiersze
1.6 KiB
Python
47 wiersze
1.6 KiB
Python
# spi_mater.py A nonblocking SPI master for RP2040/RP2350
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# Inspired by
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# https://github.com/raspberrypi/pico-micropython-examples/blob/master/pio/pio_spi.py
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# Released under the MIT License (MIT). See LICENSE.
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# Copyright (c) 2025 Peter Hinch
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import rp2
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@rp2.asm_pio(autopull=True, pull_thresh=8, sideset_init=rp2.PIO.OUT_LOW, out_init=rp2.PIO.OUT_LOW)
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def spi_out():
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wrap_target()
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set(x, 7).side(0x0)
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label("bitloop")
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out(pins, 1).side(0x0) # Stalls with CLK low while FIFO is empty
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jmp(x_dec, "bitloop").side(0x1)
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wrap()
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# Get data request channel for a SM: RP2040 datasheet 2.5.3 RP2350 12.6.4.1
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def dreq(sm, rx=False):
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d = (sm & 3) + ((sm >> 2) << 3)
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return 4 + d if rx else d
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# The callback runs when DMA is complete. This may be up to four byte times prior to
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# the SM running out of data (FIFO depth).
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class SpiMaster:
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def __init__(self, sm_num, freq, sck, mosi, callback):
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self._sm_num = sm_num
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self._dma = rp2.DMA()
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self._dma.irq(handler=callback, hard=True) # Assign callback
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dc = dreq(sm_num) # Data request channel
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# Transfer bytes, don't increment the write address, irq at end, and pace the transfer.
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self._ctrl = self._dma.pack_ctrl(size=0, inc_write=False, irq_quiet=False, treq_sel=dc)
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f = 2 * freq # 2 clock cycles per bit
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self._sm = rp2.StateMachine(sm_num, spi_out, freq=f, sideset_base=sck, out_base=mosi)
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self._sm.active(1)
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def deinit(self):
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self._dma.active(0)
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self._sm.active(0)
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def write(self, data):
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self._dma.config(read=data, write=self._sm, count=len(data), ctrl=self._ctrl, trigger=True)
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