kopia lustrzana https://github.com/peterhinch/micropython-samples
SPI master supports MISO transfers.
Peter Hinch
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rp2/RP2.md
41
rp2/RP2.md
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@ -7,6 +7,7 @@ These are intended to demonstrate the use of Pico-specific hardware.
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1.2 [Constructor](./RP2.md#12-constructor)
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1.3 [Methods](./RP2.md#13-methods)
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1.4 [CS](./RP2.md#14-cs) How to control the CS/ pin.
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1.5 [Callback](./RP2.md#15-callback) Notification of transfer complete.
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2. [Nonblocking SPI slave](./RP2.md#2-nonblocking-spi-slave) High speed bulk data input.
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2.1 [Introduction](./RP2.md#21-introduction)
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2.2 [SpiSlave class](./RP2.md#22-spislave-class)
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@ -36,11 +37,12 @@ They will be installed in directories:
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# 1. Nonblocking SPI master
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The module `spi_master` provides a class `SpiMaster` which uses DMA to perform
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fast SPI output. A typical use case is to transfer the contents of a frame
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buffer to a display as a background task. The following files are provided in
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the `spi` directory:
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fast SPI I/O. A typical use case is to transfer the contents of a frame buffer
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to a display as a background task. The following files are provided in the `spi`
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directory:
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* `spi_master.py` The main module.
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* `master_test.py` Test script - requires a scope or LA to check SPI output.
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* `master_test.py` Test script - uses a loopback (MOSI linked to MISO) to verify
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the master.
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* `master_slave_test.py` Full test of master linked to slave, with the latter
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printing results.
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@ -51,10 +53,11 @@ those on the official class are highly quantised, with (for example) 20MHz
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manifesting as 12MHz. The module has been tested to 30MHz, but higher rates
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should be possible.
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To run the full test, the following pins should be linked:
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* 0-19 MOSI
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To run the tests, the following pins should be linked:
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* 0-19 MOSI (master-slave links).
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* 1-18 SCK
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* 2-17 CSN
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* 16-19 MOSI-MISO (only needed for master_test.py).
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To run a test issue (e.g.):
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```py
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@ -68,13 +71,15 @@ To run a test issue (e.g.):
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This takes the following positional args:
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* `sm_num` State machine no. (0..7 on RP2040, 0..11 on RP2350)
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* `freq` SPI clock frequency in Hz.
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* `sck` A `Pin` instance for `sck`. Pins are arbitrary.
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* `mosi` A `Pin` instance for `mosi`.
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* `callback` A callback to run when DMA is complete. This is run in a hard IRQ
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context. Typical use is to set a `ThreadSafeFlag`. Note that the DMA completes
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before transmission ends due to bytes stored in the SM FIFO. This is unlikely to
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have practical consequences because of MicroPython latency: in particular
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response to a `ThreadSafeFlag` typically takes >200μs.
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* `sck` An output `Pin` instance for `sck`. Pins are arbitrary.
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* `mosi` An output `Pin` instance for `mosi`.
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* `callback` A callback to run when DMA is complete. See [below](./RP2.md#15-callback).
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Optional keyword args, for the case where data coming from the slave must be
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acquired (MISO):
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* `miso` A `Pin` instance for MISO (defined as input).
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* `ibuf` A `bytearray` for MISO data. If the quantity of data exceeds the length
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of the buffer it will be truncated.
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## 1.3 Methods
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@ -89,6 +94,16 @@ it after transmission is complete. An external pullup resistor to 3.3V should be
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provided to ensure that the receiving device sees CS/ `False` in the interval
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between power-up and application start-up. A value of a few KΩ is suggested.
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## 1.5 Callback
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This runs when the DMA is complete. It takes no args and runs in a hard IRQ
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context. Typical use is to set a `ThreadSafeFlag`, allowing a pending task to
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resume. Typically this will deassert `CS/` and initiate processing of received
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data. Note that the DMA completes before transmission ends due to bytes stored
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in the SM FIFO. This is unlikely to have practical consequences because of
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MicroPython latency: the master executes several MP instructions before the
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callback runs, and the response to a `ThreadSafeFlag` typically takes >200μs.
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# 2. Nonblocking SPI slave
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This module requires incoming data to conform to the most common SPI case, being
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@ -17,7 +17,7 @@ from .spi_master import SpiMaster
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tsf = asyncio.ThreadSafeFlag()
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def callback(dma): # Hard ISR
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def callback(): # Hard ISR
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tsf.set() # Flag user code that transfer is complete
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@ -12,15 +12,18 @@ from .spi_master import SpiMaster
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pin_cs = Pin(20, Pin.OUT, value=1)
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pin_sck = Pin(18, Pin.OUT, value=0)
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pin_mosi = Pin(19, Pin.OUT, value=0)
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pin_miso = Pin(16, Pin.IN)
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tsf = asyncio.ThreadSafeFlag()
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def callback(dma): # Hard ISR
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def callback(): # Hard ISR
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tsf.set() # Flag user code that transfer is complete
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print("cb")
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spi = SpiMaster(6, 1_000_000, pin_sck, pin_mosi, callback)
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buf = bytearray(100)
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spi = SpiMaster(6, 1_000_000, pin_sck, pin_mosi, callback, miso=pin_miso, ibuf=buf)
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async def send(data):
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@ -31,13 +34,15 @@ async def send(data):
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async def main():
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src_data = b"\xFF\x55\xAA\x00the quick brown fox jumps over the lazy dog"
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src_data = bytearray(b"\xFF\x55\xAA\x00the quick brown fox jumps over the lazy dog")
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n = 0
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while True:
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asyncio.create_task(send(src_data)) # Send as a background task
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await asyncio.sleep(1)
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print(n)
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print(n, buf[: len(src_data)])
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n += 1
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n &= 0xFF
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src_data[0] = n
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try:
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@ -5,9 +5,16 @@
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# Released under the MIT License (MIT). See LICENSE.
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# Copyright (c) 2025 Peter Hinch
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# API
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# .write() is the only way to send data. If constucted with an input buffer, any data
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# received from the slave (MISO) will be captured. Incoming data is truncated to fit buffer.
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import rp2
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from micropython import alloc_emergency_exception_buf
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alloc_emergency_exception_buf(100)
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# Output-only SM
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@rp2.asm_pio(autopull=True, pull_thresh=8, sideset_init=rp2.PIO.OUT_LOW, out_init=rp2.PIO.OUT_LOW)
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def spi_out():
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wrap_target()
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@ -18,6 +25,26 @@ def spi_out():
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wrap()
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# Version accepts incoming data
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@rp2.asm_pio(
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autopull=True,
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autopush=True,
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pull_thresh=8,
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push_thresh=8,
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sideset_init=rp2.PIO.OUT_LOW,
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out_init=rp2.PIO.OUT_LOW,
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)
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def spi_inout():
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wrap_target()
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set(x, 7).side(0x0)
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label("bitloop")
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out(pins, 1).side(0x0) # Stalls with CLK low while FIFO is empty
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mov(y, y).side(0x1) # Set clock high
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in_(pins, 1).side(0x1)
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jmp(x_dec, "bitloop").side(0x0)
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wrap()
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# Get data request channel for a SM: RP2040 datasheet 2.5.3 RP2350 12.6.4.1
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def dreq(sm, rx=False):
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d = (sm & 3) + ((sm >> 2) << 3)
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@ -27,20 +54,61 @@ def dreq(sm, rx=False):
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# The callback runs when DMA is complete. This may be up to four byte times prior to
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# the SM running out of data (FIFO depth).
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class SpiMaster:
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def __init__(self, sm_num, freq, sck, mosi, callback):
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def __init__(self, sm_num, freq, sck, mosi, callback, *, miso=None, ibuf=None):
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self._sm_num = sm_num
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self._cb = callback
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self._dma = rp2.DMA()
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self._dma.irq(handler=callback, hard=True) # Assign callback
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self._dma.irq(handler=self._done, hard=True) # Assign callback
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dc = dreq(sm_num) # Data request channel
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# Transfer bytes, don't increment the write address, irq at end, and pace the transfer.
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self._ctrl = self._dma.pack_ctrl(size=0, inc_write=False, irq_quiet=False, treq_sel=dc)
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f = 2 * freq # 2 clock cycles per bit
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self._sm = rp2.StateMachine(sm_num, spi_out, freq=f, sideset_base=sck, out_base=mosi)
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self._io = 0 if ibuf is None else len(ibuf)
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self._ibuf = ibuf
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if ibuf is None: # Output only
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f = 2 * freq # 2 clock cycles per bit
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self._sm = rp2.StateMachine(sm_num, spi_out, freq=f, sideset_base=sck, out_base=mosi)
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self._sm.active(1)
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else:
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# I/O
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f = 4 * freq # 4 cycles per bit
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self._sm = rp2.StateMachine(
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sm_num,
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spi_inout,
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freq=f,
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sideset_base=sck,
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out_base=mosi,
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in_base=miso,
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)
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self._idma = rp2.DMA()
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dc = dreq(sm_num, True) # Data in
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self._ictrl = self._idma.pack_ctrl(
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size=0, inc_read=False, irq_quiet=False, treq_sel=dc
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)
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# self._idma.irq(self._done)
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self._sm.active(1)
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def deinit(self):
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def _done(self, dma): # I/O transfer complete
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self._dma.active(0)
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self._sm.restart()
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if self._io:
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self._idma.active(0)
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self._sm.active(0)
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self._cb()
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# callback = self._cb
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# callback()
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def write(self, data):
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self._dma.config(read=data, write=self._sm, count=len(data), ctrl=self._ctrl, trigger=True)
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ld = len(data)
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self._dma.config(read=data, write=self._sm, count=ld, ctrl=self._ctrl)
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self._dma.active(1)
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if self._io:
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cnt = min(ld, self._io) # Prevent overrun of ibuf
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self._idma.config(read=self._sm, write=self._ibuf, count=cnt, ctrl=self._ictrl)
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self._idma.active(1)
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self._sm.active(1) # Start SM
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def deinit(self):
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self._dma.close()
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self._sm.active(0)
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if self._io:
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self._idma.close()
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