kopia lustrzana https://github.com/sq2ips/m20-custom-firmware
344 wiersze
12 KiB
C
344 wiersze
12 KiB
C
/*
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* adf.c
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* Based on https://github.com/adamgreig/wombat
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* Adapted by SQ2DK
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*/
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#include "adf.h"
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#include "config.h"
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#include "main.h"
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// Configuration storage structs =============================================
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struct {
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struct {
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uint16_t frequency_error_correction;
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uint8_t r_divider;
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uint8_t crystal_doubler;
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uint8_t crystal_oscillator_disable;
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uint8_t clock_out_divider;
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uint8_t vco_adjust;
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uint8_t output_divider;
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} r0;
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struct {
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uint16_t fractional_n;
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uint8_t integer_n;
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uint8_t prescaler;
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} r1;
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struct {
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uint8_t mod_control;
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uint8_t gook;
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uint8_t power_amplifier_level;
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uint16_t modulation_deviation;
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uint8_t gfsk_modulation_control;
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uint8_t index_counter;
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} r2;
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struct {
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uint8_t pll_enable;
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uint8_t pa_enable;
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uint8_t clkout_enable;
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uint8_t data_invert;
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uint8_t charge_pump_current;
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uint8_t bleed_up;
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uint8_t bleed_down;
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uint8_t vco_disable;
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uint8_t muxout;
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uint8_t ld_precision;
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uint8_t vco_bias;
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uint8_t pa_bias;
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uint8_t pll_test_mode;
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uint8_t sd_test_mode;
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} r3;
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} adf_config;
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// Prototypes for internal functions =========================================
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void adf_reset_register_zero(void);
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void adf_reset_register_one(void);
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void adf_reset_register_two(void);
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void adf_reset_register_three(void);
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void adf_reset(void);
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void adf_write_register_zero(void);
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void adf_write_register_one(void);
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void adf_write_register_two(void);
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void adf_write_register_three(void);
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void adf_write_register(uint32_t reg);
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// Configuration functions ===================================================
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// Config resetting functions --------------------------------------------
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void adf_reset_config(void) {
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adf_reset_register_zero();
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adf_reset_register_one();
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adf_reset_register_two();
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adf_reset_register_three();
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adf_reset();
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}
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/* Bellow values are based on experiments. Do not change if not required. Some
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* of those are critical and are not documented vco_adjust=3; pa_bias = 7;
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* vco_bias = 0; crystal_oscillator_disable = 1; For modulation deviation set
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* value on experimental basis, for FM channel width to be appropriate. In
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* theory in 244z steps?
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*/
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void adf_reset_register_zero(void) {
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adf_config.r0.frequency_error_correction =
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ADF_FREQ_CORRECTION; // 11Bit Freq err corr 0b10011 - or whatever reason
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// M20
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adf_config.r0.r_divider = 1;
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adf_config.r0.crystal_doubler = ADF_OFF;
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adf_config.r0.crystal_oscillator_disable =
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1; // osclator disabled - we are getting clock from STM
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adf_config.r0.clock_out_divider = 8; // 0b1000 = 8 FOR M20
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adf_config.r0.vco_adjust = 3; // maximum VCO adjust b11
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adf_config.r0.output_divider = 1; // for M20
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}
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void adf_reset_register_one(void) {
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adf_config.r1.fractional_n = 0;
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adf_config.r1.integer_n = 0;
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adf_config.r1.prescaler = ADF_PRESCALER_4_5;
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}
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void adf_reset_register_two(void) {
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adf_config.r2.mod_control = ADF_MODULATION_FSK;
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adf_config.r2.gook = ADF_OFF;
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adf_config.r2.power_amplifier_level = 0; // power level
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adf_config.r2.modulation_deviation = 2; // 5= about 5k5Hz, 10=11kHz
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// adf_config.r2.modulation_deviation = 11;
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adf_config.r2.gfsk_modulation_control = 0;
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adf_config.r2.index_counter = 0;
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}
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void adf_reset_register_three(void) {
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adf_config.r3.pll_enable = ADF_OFF;
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adf_config.r3.pa_enable = ADF_OFF;
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adf_config.r3.clkout_enable = ADF_OFF;
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adf_config.r3.data_invert = ADF_ON;
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adf_config.r3.charge_pump_current = ADF_CP_CURRENT_1_5;
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adf_config.r3.bleed_up = ADF_OFF;
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adf_config.r3.bleed_down = ADF_OFF;
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adf_config.r3.vco_disable = ADF_OFF;
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adf_config.r3.muxout = ADF_MUXOUT_REG_READY;
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adf_config.r3.ld_precision = ADF_LD_PRECISION_3_CYCLES;
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adf_config.r3.vco_bias = 0; // was 4
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adf_config.r3.pa_bias = 7;
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adf_config.r3.pll_test_mode = 0;
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adf_config.r3.sd_test_mode = 0;
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}
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void adf_reset(void) {
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LL_GPIO_ResetOutputPin(ADF_CE_GPIO_Port, ADF_CE_Pin);
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LL_GPIO_ResetOutputPin(RADIO_EN_GPIO_Port, RADIO_EN_Pin);
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LL_GPIO_ResetOutputPin(ADF_LE_GPIO_Port, ADF_LE_Pin);
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LL_GPIO_SetOutputPin(ADF_TX_Data_GPIO_Port, ADF_TX_Data_Pin);
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LL_GPIO_SetOutputPin(ADF_CLK_GPIO_Port, ADF_CLK_Pin);
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LL_GPIO_SetOutputPin(ADF_Data_GPIO_Port, ADF_Data_Pin);
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LL_mDelay(1); // short delay between powering off and on
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LL_GPIO_SetOutputPin(RADIO_EN_GPIO_Port, RADIO_EN_Pin);
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LL_GPIO_SetOutputPin(ADF_CE_GPIO_Port, ADF_CE_Pin);
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}
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void adf_turn_off(void) {
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LL_GPIO_ResetOutputPin(RADIO_EN_GPIO_Port,
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RADIO_EN_Pin); // TODO - check power consumption. Check
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// if registry is gone.
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LL_GPIO_ResetOutputPin(ADF_CE_GPIO_Port, ADF_CE_Pin);
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}
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// Configuration writing functions ---------------------------------------
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void adf_write_config(void) {
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adf_write_register_zero();
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adf_write_register_one();
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adf_write_register_two();
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adf_write_register_three();
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}
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void adf_write_register_zero(void) {
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uint32_t reg = (0) |
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((adf_config.r0.frequency_error_correction & 0x7FF) << 2) |
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((adf_config.r0.r_divider & 0xF) << 13) |
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((adf_config.r0.crystal_doubler & 0x1) << 17) |
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((adf_config.r0.crystal_oscillator_disable & 0x1) << 18) |
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((adf_config.r0.clock_out_divider & 0xF) << 19) |
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((adf_config.r0.vco_adjust & 0x3) << 23) |
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((adf_config.r0.output_divider & 0x3) << 25);
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adf_write_register(reg);
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}
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void adf_write_register_one(void) {
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uint32_t reg = (1) | ((adf_config.r1.fractional_n & 0xFFF) << 2) |
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((adf_config.r1.integer_n & 0xFF) << 14) |
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((adf_config.r1.prescaler & 0x1) << 22);
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adf_write_register(reg);
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}
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void adf_write_register_two(void) {
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uint32_t reg = (2) | ((adf_config.r2.mod_control & 0x3) << 2) |
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((adf_config.r2.gook & 0x1) << 4) |
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((adf_config.r2.power_amplifier_level & 0x3F) << 5) |
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((adf_config.r2.modulation_deviation & 0x1FF) << 11) |
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((adf_config.r2.gfsk_modulation_control & 0x7) << 20) |
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((adf_config.r2.index_counter & 0x3) << 23);
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adf_write_register(reg);
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}
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void adf_write_register_three(void) {
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uint32_t reg = (3) | ((adf_config.r3.pll_enable & 0x1) << 2) |
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((adf_config.r3.pa_enable & 0x1) << 3) |
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((adf_config.r3.clkout_enable & 0x1) << 4) |
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((adf_config.r3.data_invert & 0x1) << 5) |
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((adf_config.r3.charge_pump_current & 0x3) << 6) |
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((adf_config.r3.bleed_up & 0x1) << 8) |
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((adf_config.r3.bleed_down & 0x1) << 9) |
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((adf_config.r3.vco_disable & 0x1) << 10) |
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((adf_config.r3.muxout & 0xF) << 11) |
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((adf_config.r3.ld_precision & 0x1) << 15) |
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((adf_config.r3.vco_bias & 0xF) << 16) |
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((adf_config.r3.pa_bias & 0x7) << 20) |
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((adf_config.r3.pll_test_mode & 0x1F) << 23) |
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((adf_config.r3.sd_test_mode & 0xF) << 28);
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adf_write_register(reg);
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}
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void adf_write_register(uint32_t data) {
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/*
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* Below procedure is not the prettiest one, but it works. Lots of work was
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* put into it, so be careful when changing. wl value might be changed - delay
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* is implemented, since other ways did not worked. It is possible, that they
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* are not required, or that they would have to be adjusted if CPU frequency
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* would be adjusted.
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*/
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uint16_t wl = 5; // wl=10;
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LL_GPIO_SetOutputPin(ADF_LE_GPIO_Port, ADF_LE_Pin);
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for (uint16_t n = 0; n < (wl * 2); n++)
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asm("NOP");
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LL_GPIO_ResetOutputPin(ADF_LE_GPIO_Port, ADF_LE_Pin);
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LL_GPIO_ResetOutputPin(ADF_Data_GPIO_Port, ADF_Data_Pin);
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LL_GPIO_ResetOutputPin(ADF_CLK_GPIO_Port, ADF_CLK_Pin);
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for (uint16_t n = 0; n < wl; n++)
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asm("NOP");
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for (int i = 0; i < 32; i++) {
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LL_GPIO_ResetOutputPin(ADF_CLK_GPIO_Port, ADF_CLK_Pin);
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if (data & 0b10000000000000000000000000000000) {
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LL_GPIO_SetOutputPin(ADF_Data_GPIO_Port, ADF_Data_Pin);
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} else {
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LL_GPIO_ResetOutputPin(ADF_Data_GPIO_Port, ADF_Data_Pin);
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}
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for (uint16_t n = 0; n < (wl * 2); n++)
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asm("NOP");
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LL_GPIO_SetOutputPin(ADF_CLK_GPIO_Port, ADF_CLK_Pin);
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data = data << 1;
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}
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LL_GPIO_SetOutputPin(ADF_LE_GPIO_Port, ADF_LE_Pin);
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for (uint16_t n = 0; n < (wl * 2); n++)
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asm("NOP");
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LL_GPIO_ResetOutputPin(ADF_CLK_GPIO_Port, ADF_CLK_Pin);
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LL_GPIO_ResetOutputPin(ADF_LE_GPIO_Port, ADF_LE_Pin);
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}
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// Configuration setting functions ---------------------------------------
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void adf_set_frequency_error_correction(uint16_t error) {
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adf_config.r0.frequency_error_correction = error;
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}
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void adf_set_r_divider(uint8_t r) { adf_config.r0.r_divider = r; }
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void adf_set_vco_adjust(uint8_t adjust) { adf_config.r0.vco_adjust = adjust; }
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void adf_set_frequency(float freq) {
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float latch = freq / ADF_CLOCK; // changed for 9MHz input
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uint32_t Nint = latch;
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latch = latch - Nint;
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uint32_t Nfrac = latch * 4096;
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adf_set_n(Nint);
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adf_set_m((uint16_t)Nfrac);
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}
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void adf_4fsk_fone(uint8_t tone) {
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/* minimum frequency change is defined as Fpfd/(2^15). Fpfd=osc/Rdiv (Rdiv=1
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* in our case). Thus for achieving 244Hz frequency step we have to provide
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* 8MHz osc signal using frequency adjust register is fastest, since one have
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* to write only register 0 (consecutive registers does not need to be sent)
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* Frequency shifts smaller than calculated cannot be achieved, thus baudrate
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* slower than 100bd are not possible. Only multiplications of 100bd are
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* alowed with standard tone spacings
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*/
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uint16_t freq_corr_regist_tmp =
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adf_config.r0
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.frequency_error_correction; // Temporarily store correction value, as
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// we are going to change it
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adf_config.r0.frequency_error_correction =
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adf_config.r0.frequency_error_correction +
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tone; // add tone space to current freq corr.
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adf_write_register_zero(); // write reg0. no other registers have to be
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// changed.
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adf_config.r0.frequency_error_correction =
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freq_corr_regist_tmp; // restore original value
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}
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void adf_set_n(uint8_t n) { adf_config.r1.integer_n = n; }
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void adf_set_m(uint16_t m) { adf_config.r1.fractional_n = m; }
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void adf_set_pa_level(uint8_t level) {
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adf_config.r2.power_amplifier_level = level;
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}
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void adf_set_pll_enable(uint8_t enable) { adf_config.r3.pll_enable = enable; }
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void adf_set_pa_enable(uint8_t enable) { adf_config.r3.pa_enable = enable; }
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void adf_setup(void) {
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LL_GPIO_SetOutputPin(ADF_CE_GPIO_Port, ADF_CE_Pin);
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adf_reset_config();
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adf_set_r_divider(
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1); // We will be using whole 8MHz for freq reference for adf7012
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adf_set_frequency(QRG_FSK4[0]); // Temporarily set freq for CW - it is going
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// to be changed later when turning on TX
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adf_set_pll_enable(ADF_ON);
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adf_write_config();
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}
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void adf_RF_on(
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float freq,
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uint8_t power) { // arguments are TX frequency (Hz) and power level (0-63)
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LL_GPIO_SetOutputPin(ADF_CE_GPIO_Port, ADF_CE_Pin);
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adf_set_frequency(freq);
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adf_set_pa_enable(ADF_ON);
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adf_set_pa_level(power);
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adf_write_config();
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if (RF_BOOST_ACTIVE) {
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LL_GPIO_ResetOutputPin(RF_Boost_GPIO_Port, RF_Boost_Pin);
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} else {
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LL_GPIO_SetOutputPin(RF_Boost_GPIO_Port, RF_Boost_Pin);
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}
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// boost 0 - is ON adf_write_register_three();
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}
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void adf_RF_off(void) {
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adf_set_pa_enable(ADF_OFF);
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adf_set_pa_level(0);
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adf_write_config();
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LL_GPIO_SetOutputPin(
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RF_Boost_GPIO_Port,
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RF_Boost_Pin); // boost pin high for RF power off. Reduces power by ~15dB
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}
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// MUX pin is not connected in M20
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