kopia lustrzana https://github.com/cnlohr/lolra
135 wiersze
5.0 KiB
C
135 wiersze
5.0 KiB
C
/*
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MIT License
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Copyright (c) 2024 Charles Lohr "CNLohr"
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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*/
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#ifndef _ESP8266_I2S_SETUP
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#define _ESP8266_I2S_SETUP
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#include "slc_register.h"
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#include "dmastuff.h"
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/* Need something like:
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#define DMABUFFERDEPTH 3
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#define WS_I2S_BCK SPI_DIV //Can't be less than 1.
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#define WS_I2S_DIV 1
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*/
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static struct sdio_queue i2sBufDescTX[DMABUFFERDEPTH] __attribute__((aligned(128)));;
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void slc_isr(void * v);
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static void testi2s_init( uint32_t * initial_data );
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//Initialize I2S subsystem for DMA circular buffer use
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static void testi2s_init( uint32_t * default_data ) {
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int x, y;
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//Bits are shifted out
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//Initialize DMA buffer descriptors in such a way that they will form a circular
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//buffer.
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for (x=0; x<DMABUFFERDEPTH; x++) {
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i2sBufDescTX[x].owner=1;
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i2sBufDescTX[x].eof=1; // Trigger interrupt on packet complete.
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i2sBufDescTX[x].sub_sof=0;
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i2sBufDescTX[x].datalen=DMA_SIZE_WORDS*4;
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i2sBufDescTX[x].blocksize=4;
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i2sBufDescTX[x].buf_ptr= ((uint32_t)default_data);
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i2sBufDescTX[x].unused=0;
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i2sBufDescTX[x].next_link_ptr=(int)((x<(DMABUFFERDEPTH-1))?(&i2sBufDescTX[x+1]):(&i2sBufDescTX[0]));
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}
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//Reset DMA )
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//SLC_TX_LOOP_TEST = IF this isn't set, SO will occasionally get unrecoverable errors when you underflow.
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//Originally this little tidbit was found at https://github.com/pvvx/esp8266web/blob/master/info/libs/bios/sip_slc.c
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//
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//I have not tried without SLC_AHBM_RST | SLC_AHBM_FIFO_RST. I just assume they are useful?
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SET_PERI_REG_MASK(SLC_CONF0, SLC_TX_LOOP_TEST |SLC_RXLINK_RST|SLC_TXLINK_RST|SLC_AHBM_RST | SLC_AHBM_FIFO_RST);
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CLEAR_PERI_REG_MASK(SLC_CONF0, SLC_RXLINK_RST|SLC_TXLINK_RST|SLC_AHBM_RST | SLC_AHBM_FIFO_RST);
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//Clear DMA int flags
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SET_PERI_REG_MASK(SLC_INT_CLR, 0xffffffff);
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CLEAR_PERI_REG_MASK(SLC_INT_CLR, 0xffffffff);
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//Enable and configure DMA
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CLEAR_PERI_REG_MASK(SLC_CONF0, (SLC_MODE<<SLC_MODE_S));
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SET_PERI_REG_MASK(SLC_CONF0,(1<<SLC_MODE_S));
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// We have to do this, otherwise, when the end of a "RX" packet is hit, it will skip outputting a few random frames.
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SET_PERI_REG_MASK(SLC_RX_DSCR_CONF,SLC_INFOR_NO_REPLACE|SLC_TOKEN_NO_REPLACE);
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CLEAR_PERI_REG_MASK(SLC_RX_DSCR_CONF, SLC_RX_FILL_EN|SLC_RX_EOF_MODE | SLC_RX_FILL_MODE);
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CLEAR_PERI_REG_MASK(SLC_RX_LINK,SLC_RXLINK_DESCADDR_MASK);
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SET_PERI_REG_MASK(SLC_RX_LINK, ((uint32)&i2sBufDescTX[0]) & SLC_RXLINK_DESCADDR_MASK);
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//Attach the DMA interrupt
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ets_isr_attach(ETS_SLC_INUM, slc_isr, 0);
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WRITE_PERI_REG(SLC_INT_ENA, SLC_RX_EOF_INT_ENA ); // Not including SLC_RX_UDF_INT_ENA
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//clear any interrupt flags that are set
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WRITE_PERI_REG(SLC_INT_CLR, 0xffffffff);
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///enable DMA intr in cpu
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ets_isr_unmask(1<<ETS_SLC_INUM);
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//Start transmission
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SET_PERI_REG_MASK(SLC_RX_LINK, SLC_RXLINK_START);
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//Init pins to i2s functions
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_I2SO_DATA); // GPIO3
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// PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_I2SO_WS); // GPIO2
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// PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_I2SO_BCK); // GPIO15
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//Enable clock to i2s subsystem
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i2c_writeReg_Mask_def(i2c_bbpll, i2c_bbpll_en_audio_clock_out, 1);
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//Reset I2S subsystem
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CLEAR_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
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SET_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
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CLEAR_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
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CLEAR_PERI_REG_MASK(I2S_FIFO_CONF, I2S_I2S_DSCR_EN|(I2S_I2S_RX_FIFO_MOD<<I2S_I2S_RX_FIFO_MOD_S));
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SET_PERI_REG_MASK(I2S_FIFO_CONF, I2S_I2S_DSCR_EN);
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WRITE_PERI_REG(I2SRXEOF_NUM, DMA_SIZE_WORDS*4);
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CLEAR_PERI_REG_MASK(I2SCONF_CHAN, (I2S_RX_CHAN_MOD<<I2S_RX_CHAN_MOD_S));
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CLEAR_PERI_REG_MASK(I2SCONF, I2S_TRANS_SLAVE_MOD|I2S_RECE_SLAVE_MOD|
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(I2S_BITS_MOD<<I2S_BITS_MOD_S)|
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(I2S_BCK_DIV_NUM <<I2S_BCK_DIV_NUM_S)|
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(I2S_CLKM_DIV_NUM<<I2S_CLKM_DIV_NUM_S));
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SET_PERI_REG_MASK(I2SCONF, I2S_RIGHT_FIRST|I2S_MSB_RIGHT|
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I2S_RECE_MSB_SHIFT|I2S_TRANS_MSB_SHIFT|
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((WS_I2S_BCK&I2S_BCK_DIV_NUM )<<I2S_BCK_DIV_NUM_S)|
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((WS_I2S_DIV&I2S_CLKM_DIV_NUM)<<I2S_CLKM_DIV_NUM_S) );
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//Start transmission
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SET_PERI_REG_MASK(I2SCONF,I2S_I2S_TX_START|I2S_I2S_RX_START);
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}
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#endif
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