kopia lustrzana https://github.com/espressif/esp-idf
357 wiersze
16 KiB
C
357 wiersze
16 KiB
C
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "sdkconfig.h"
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#if CONFIG_I2S_ENABLE_DEBUG_LOG
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// The local log level must be defined before including esp_log.h
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// Set the maximum log level for this source file
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#define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
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#endif
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#include "hal/i2s_hal.h"
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#include "driver/gpio.h"
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#include "driver/i2s_std.h"
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#include "i2s_private.h"
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#include "clk_ctrl_os.h"
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#include "esp_intr_alloc.h"
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#include "esp_check.h"
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const static char *TAG = "i2s_std";
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static esp_err_t i2s_std_calculate_clock(i2s_chan_handle_t handle, const i2s_std_clk_config_t *clk_cfg, i2s_hal_clock_info_t *clk_info)
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{
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uint32_t rate = clk_cfg->sample_rate_hz;
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i2s_std_slot_config_t *slot_cfg = &((i2s_std_config_t *)(handle->mode_info))->slot_cfg;
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uint32_t slot_bits = (slot_cfg->slot_bit_width == I2S_SLOT_BIT_WIDTH_AUTO) ||
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((int)slot_cfg->slot_bit_width < (int)slot_cfg->data_bit_width) ?
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slot_cfg->data_bit_width : slot_cfg->slot_bit_width;
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/* Calculate multiple
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* Fmclk = bck_div*fbck = fsclk/(mclk_div+b/a) */
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if (handle->role == I2S_ROLE_MASTER) {
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clk_info->bclk = rate * handle->total_slot * slot_bits;
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clk_info->mclk = rate * clk_cfg->mclk_multiple;
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clk_info->bclk_div = clk_info->mclk / clk_info->bclk;
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} else {
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/* For slave mode, mclk >= bclk * 8, so fix bclk_div to 2 first */
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clk_info->bclk_div = 8;
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clk_info->bclk = rate * handle->total_slot * slot_bits;
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clk_info->mclk = clk_info->bclk * clk_info->bclk_div;
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}
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#if SOC_I2S_SUPPORTS_APLL
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clk_info->sclk = (clk_cfg->clk_src == I2S_CLK_SRC_APLL) ? i2s_set_get_apll_freq(clk_info->mclk) : I2S_LL_BASE_CLK;
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#else
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clk_info->sclk = I2S_LL_BASE_CLK;
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#endif
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clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
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/* Check if the configuration is correct */
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ESP_RETURN_ON_FALSE(clk_info->mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
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return ESP_OK;
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}
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static esp_err_t i2s_std_set_clock(i2s_chan_handle_t handle, const i2s_std_clk_config_t *clk_cfg)
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{
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esp_err_t ret = ESP_OK;
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i2s_std_config_t *std_cfg = (i2s_std_config_t *)(handle->mode_info);
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ESP_RETURN_ON_FALSE(std_cfg->slot_cfg.data_bit_width != I2S_DATA_BIT_WIDTH_24BIT ||
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(clk_cfg->mclk_multiple % 3 == 0), ESP_ERR_INVALID_ARG, TAG,
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"The 'mclk_multiple' should be the multiple of 3 while using 24-bit data width");
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i2s_hal_clock_info_t clk_info;
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/* Calculate clock parameters */
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ESP_RETURN_ON_ERROR(i2s_std_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed");
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ESP_LOGD(TAG, "Clock division info: [sclk] %d Hz [mdiv] %d [mclk] %d Hz [bdiv] %d [bclk] %d Hz",
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clk_info.sclk, clk_info.mclk_div, clk_info.mclk, clk_info.bclk_div, clk_info.bclk);
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portENTER_CRITICAL(&g_i2s.spinlock);
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/* Set clock configurations in HAL*/
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if (handle->dir == I2S_DIR_TX) {
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i2s_hal_set_tx_clock(&handle->controller->hal, &clk_info, clk_cfg->clk_src);
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} else {
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i2s_hal_set_rx_clock(&handle->controller->hal, &clk_info, clk_cfg->clk_src);
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}
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portEXIT_CRITICAL(&g_i2s.spinlock);
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/* Update the mode info: clock configuration */
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memcpy(&(std_cfg->clk_cfg), clk_cfg, sizeof(i2s_std_clk_config_t));
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return ret;
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}
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static esp_err_t i2s_std_set_slot(i2s_chan_handle_t handle, const i2s_std_slot_config_t *slot_cfg)
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{
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/* Update the total slot num and active slot num */
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handle->total_slot = 2;
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handle->active_slot = slot_cfg->slot_mode == I2S_SLOT_MODE_MONO ? 1 : 2;
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uint32_t buf_size = i2s_get_buf_size(handle, slot_cfg->data_bit_width, handle->dma.frame_num);
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/* The DMA buffer need to re-allocate if the buffer size changed */
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if (handle->dma.buf_size != buf_size) {
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handle->dma.buf_size = buf_size;
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ESP_RETURN_ON_ERROR(i2s_free_dma_desc(handle), TAG, "failed to free the old dma descriptor");
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ESP_RETURN_ON_ERROR(i2s_alloc_dma_desc(handle, handle->dma.desc_num, buf_size),
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TAG, "allocate memory for dma descriptor failed");
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}
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bool is_slave = handle->role == I2S_ROLE_SLAVE;
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/* Share bck and ws signal in full-duplex mode */
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if (handle->controller->full_duplex) {
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i2s_ll_share_bck_ws(handle->controller->hal.dev, true);
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/* Since bck and ws are shared, only tx or rx can be master
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Force to set rx as slave to avoid conflict of clock signal */
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if (handle->dir == I2S_DIR_RX) {
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is_slave = true;
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}
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} else {
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i2s_ll_share_bck_ws(handle->controller->hal.dev, false);
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}
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portENTER_CRITICAL(&g_i2s.spinlock);
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/* Configure the hardware to apply STD format */
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if (handle->dir == I2S_DIR_TX) {
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i2s_hal_std_set_tx_slot(&(handle->controller->hal), is_slave, (i2s_hal_slot_config_t *)slot_cfg);
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} else {
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i2s_hal_std_set_rx_slot(&(handle->controller->hal), is_slave, (i2s_hal_slot_config_t *)slot_cfg);
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}
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portEXIT_CRITICAL(&g_i2s.spinlock);
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/* Update the mode info: slot configuration */
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i2s_std_config_t *std_cfg = (i2s_std_config_t *)(handle->mode_info);
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memcpy(&(std_cfg->slot_cfg), slot_cfg, sizeof(i2s_std_slot_config_t));
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return ESP_OK;
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}
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static esp_err_t i2s_std_set_gpio(i2s_chan_handle_t handle, const i2s_std_gpio_config_t *gpio_cfg)
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{
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int id = handle->controller->id;
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/* Check validity of selected pins */
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ESP_RETURN_ON_FALSE((gpio_cfg->bclk == -1 || GPIO_IS_VALID_GPIO(gpio_cfg->bclk)),
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ESP_ERR_INVALID_ARG, TAG, "bclk invalid");
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ESP_RETURN_ON_FALSE((gpio_cfg->ws == -1 || GPIO_IS_VALID_GPIO(gpio_cfg->ws)),
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ESP_ERR_INVALID_ARG, TAG, "ws invalid");
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i2s_std_config_t *std_cfg = (i2s_std_config_t *)(handle->mode_info);
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/* Loopback if dout = din */
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if (gpio_cfg->dout != -1 &&
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gpio_cfg->dout == gpio_cfg->din) {
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i2s_gpio_loopback_set(gpio_cfg->dout, i2s_periph_signal[id].data_out_sig, i2s_periph_signal[id].data_in_sig);
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} else if (handle->dir == I2S_DIR_TX) {
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/* Set data output GPIO */
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i2s_gpio_check_and_set(gpio_cfg->dout, i2s_periph_signal[id].data_out_sig, false, false);
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} else {
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/* Set data input GPIO */
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i2s_gpio_check_and_set(gpio_cfg->din, i2s_periph_signal[id].data_in_sig, true, false);
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}
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if (handle->role == I2S_ROLE_SLAVE) {
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/* For "tx + slave" mode, select TX signal index for ws and bck */
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if (handle->dir == I2S_DIR_TX && !handle->controller->full_duplex) {
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#if SOC_I2S_HW_VERSION_2
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i2s_ll_mclk_bind_to_tx_clk(handle->controller->hal.dev);
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#endif
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i2s_gpio_check_and_set(gpio_cfg->ws, i2s_periph_signal[id].s_tx_ws_sig, true, gpio_cfg->invert_flags.ws_inv);
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i2s_gpio_check_and_set(gpio_cfg->bclk, i2s_periph_signal[id].s_tx_bck_sig, true, gpio_cfg->invert_flags.bclk_inv);
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/* For "tx + rx + slave" or "rx + slave" mode, select RX signal index for ws and bck */
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} else {
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i2s_gpio_check_and_set(gpio_cfg->ws, i2s_periph_signal[id].s_rx_ws_sig, true, gpio_cfg->invert_flags.ws_inv);
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i2s_gpio_check_and_set(gpio_cfg->bclk, i2s_periph_signal[id].s_rx_bck_sig, true, gpio_cfg->invert_flags.bclk_inv);
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}
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} else {
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/* mclk only available in master mode */
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#if SOC_I2S_SUPPORTS_APLL
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bool is_apll = std_cfg->clk_cfg.clk_src == I2S_CLK_SRC_APLL;
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#else
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bool is_apll = false;
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#endif
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ESP_RETURN_ON_ERROR(i2s_check_set_mclk(id, gpio_cfg->mclk, is_apll, gpio_cfg->invert_flags.mclk_inv), TAG, "mclk config failed");
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/* For "rx + master" mode, select RX signal index for ws and bck */
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if (handle->dir == I2S_DIR_RX && !handle->controller->full_duplex) {
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#if SOC_I2S_HW_VERSION_2
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i2s_ll_mclk_bind_to_rx_clk(handle->controller->hal.dev);
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#endif
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i2s_gpio_check_and_set(gpio_cfg->ws, i2s_periph_signal[id].m_rx_ws_sig, false, gpio_cfg->invert_flags.ws_inv);
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i2s_gpio_check_and_set(gpio_cfg->bclk, i2s_periph_signal[id].m_rx_bck_sig, false, gpio_cfg->invert_flags.bclk_inv);
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/* For "tx + rx + master" or "tx + master" mode, select TX signal index for ws and bck */
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} else {
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i2s_gpio_check_and_set(gpio_cfg->ws, i2s_periph_signal[id].m_tx_ws_sig, false, gpio_cfg->invert_flags.ws_inv);
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i2s_gpio_check_and_set(gpio_cfg->bclk, i2s_periph_signal[id].m_tx_bck_sig, false, gpio_cfg->invert_flags.bclk_inv);
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}
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}
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/* Update the mode info: gpio configuration */
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memcpy(&(std_cfg->gpio_cfg), gpio_cfg, sizeof(i2s_std_gpio_config_t));
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return ESP_OK;
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}
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esp_err_t i2s_channel_init_std_mode(i2s_chan_handle_t handle, const i2s_std_config_t *std_cfg)
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{
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#if CONFIG_I2S_ENABLE_DEBUG_LOG
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esp_log_level_set(TAG, ESP_LOG_DEBUG);
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#endif
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I2S_NULL_POINTER_CHECK(TAG, handle);
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esp_err_t ret = ESP_OK;
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xSemaphoreTake(handle->mutex, portMAX_DELAY);
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handle->mode = I2S_COMM_MODE_STD;
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/* Allocate memory for storing the configurations of standard mode */
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if (handle->mode_info) {
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free(handle->mode_info);
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}
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handle->mode_info = calloc(1, sizeof(i2s_std_config_t));
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ESP_GOTO_ON_FALSE(handle->mode_info, ESP_ERR_NO_MEM, err, TAG, "no memory for storing the configurations");
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ESP_GOTO_ON_FALSE(handle->state == I2S_CHAN_STATE_REGISTER, ESP_ERR_INVALID_STATE, err, TAG, "the channel has initialized already");
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ESP_GOTO_ON_ERROR(i2s_std_set_gpio(handle, &std_cfg->gpio_cfg), err, TAG, "initialize channel failed while setting gpio pins");
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/* i2s_set_std_slot should be called before i2s_set_std_clock while initializing, because clock is relay on the slot */
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ESP_GOTO_ON_ERROR(i2s_std_set_slot(handle, &std_cfg->slot_cfg), err, TAG, "initialize channel failed while setting slot");
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#if SOC_I2S_SUPPORTS_APLL
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/* Enable APLL and acquire its lock when the clock source is APLL */
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if (std_cfg->clk_cfg.clk_src == I2S_CLK_SRC_APLL) {
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periph_rtc_apll_acquire();
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handle->apll_en = true;
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}
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#endif
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ESP_GOTO_ON_ERROR(i2s_std_set_clock(handle, &std_cfg->clk_cfg), err, TAG, "initialize channel failed while setting clock");
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ESP_GOTO_ON_ERROR(i2s_init_dma_intr(handle, ESP_INTR_FLAG_LEVEL1), err, TAG, "initialize dma interrupt failed");
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#if SOC_I2S_HW_VERSION_2
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/* Enable clock to start outputting mclk signal. Some codecs will reset once mclk stop */
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if (handle->dir == I2S_DIR_TX) {
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i2s_ll_tx_enable_std(handle->controller->hal.dev);
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i2s_ll_tx_enable_clock(handle->controller->hal.dev);
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} else {
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i2s_ll_rx_enable_std(handle->controller->hal.dev);
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i2s_ll_rx_enable_clock(handle->controller->hal.dev);
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}
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#endif
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#ifdef CONFIG_PM_ENABLE
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esp_pm_lock_type_t pm_type = ESP_PM_APB_FREQ_MAX;
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#if SOC_I2S_SUPPORTS_APLL
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if (std_cfg->clk_cfg.clk_src == I2S_CLK_SRC_APLL) {
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pm_type = ESP_PM_NO_LIGHT_SLEEP;
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}
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#endif // SOC_I2S_SUPPORTS_APLL
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ESP_RETURN_ON_ERROR(esp_pm_lock_create(pm_type, 0, "i2s_driver", &handle->pm_lock), TAG, "I2S pm lock create failed");
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#endif
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/* Initialization finished, mark state as ready */
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handle->state = I2S_CHAN_STATE_READY;
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xSemaphoreGive(handle->mutex);
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ESP_LOGD(TAG, "The %s channel on I2S%d has been initialized to STD mode successfully",
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handle->dir == I2S_DIR_TX ? "tx" : "rx", handle->controller->id);
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return ret;
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err:
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xSemaphoreGive(handle->mutex);
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return ret;
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}
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esp_err_t i2s_channel_reconfig_std_clock(i2s_chan_handle_t handle, const i2s_std_clk_config_t *clk_cfg)
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{
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I2S_NULL_POINTER_CHECK(TAG, handle);
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I2S_NULL_POINTER_CHECK(TAG, clk_cfg);
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esp_err_t ret = ESP_OK;
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xSemaphoreTake(handle->mutex, portMAX_DELAY);
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ESP_GOTO_ON_FALSE(handle->mode == I2S_COMM_MODE_STD, ESP_ERR_INVALID_ARG, err, TAG, "this handle is not working in standard moded");
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ESP_GOTO_ON_FALSE(handle->state == I2S_CHAN_STATE_READY, ESP_ERR_INVALID_STATE, err, TAG, "invalid state, I2S should be disabled before reconfiguring the clock");
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i2s_std_config_t *std_cfg = (i2s_std_config_t *)handle->mode_info;
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ESP_GOTO_ON_FALSE(std_cfg, ESP_ERR_INVALID_STATE, err, TAG, "initialization not complete");
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#if SOC_I2S_SUPPORTS_APLL
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/* Enable APLL and acquire its lock when the clock source is changed to APLL */
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if (clk_cfg->clk_src == I2S_CLK_SRC_APLL && std_cfg->clk_cfg.clk_src != I2S_CLK_SRC_APLL) {
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periph_rtc_apll_acquire();
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handle->apll_en = true;
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}
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/* Disable APLL and release its lock when clock source is changed to 160M_PLL */
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if (clk_cfg->clk_src != I2S_CLK_SRC_APLL && std_cfg->clk_cfg.clk_src == I2S_CLK_SRC_APLL) {
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periph_rtc_apll_release();
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handle->apll_en = false;
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}
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#endif
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ESP_GOTO_ON_ERROR(i2s_std_set_clock(handle, clk_cfg), err, TAG, "update clock failed");
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#ifdef CONFIG_PM_ENABLE
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// Create/Re-create power management lock
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if (std_cfg->clk_cfg.clk_src != clk_cfg->clk_src) {
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ESP_GOTO_ON_ERROR(esp_pm_lock_delete(handle->pm_lock), err, TAG, "I2S delete old pm lock failed");
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esp_pm_lock_type_t pm_type = ESP_PM_APB_FREQ_MAX;
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#if SOC_I2S_SUPPORTS_APLL
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if (clk_cfg->clk_src == I2S_CLK_SRC_APLL) {
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pm_type = ESP_PM_NO_LIGHT_SLEEP;
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}
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#endif // SOC_I2S_SUPPORTS_APLL
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ESP_GOTO_ON_ERROR(esp_pm_lock_create(pm_type, 0, "i2s_driver", &handle->pm_lock), err, TAG, "I2S pm lock create failed");
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}
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#endif //CONFIG_PM_ENABLE
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xSemaphoreGive(handle->mutex);
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return ESP_OK;
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err:
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xSemaphoreGive(handle->mutex);
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return ret;
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}
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esp_err_t i2s_channel_reconfig_std_slot(i2s_chan_handle_t handle, const i2s_std_slot_config_t *slot_cfg)
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{
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I2S_NULL_POINTER_CHECK(TAG, handle);
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I2S_NULL_POINTER_CHECK(TAG, slot_cfg);
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esp_err_t ret = ESP_OK;
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xSemaphoreTake(handle->mutex, portMAX_DELAY);
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ESP_GOTO_ON_FALSE(handle->mode == I2S_COMM_MODE_STD, ESP_ERR_INVALID_ARG, err, TAG, "this handle is not working in standard moded");
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ESP_GOTO_ON_FALSE(handle->state == I2S_CHAN_STATE_READY, ESP_ERR_INVALID_STATE, err, TAG, "invalid state, I2S should be disabled before reconfiguring the slot");
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i2s_std_config_t *std_cfg = (i2s_std_config_t *)handle->mode_info;
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ESP_GOTO_ON_FALSE(std_cfg, ESP_ERR_INVALID_STATE, err, TAG, "initialization not complete");
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ESP_GOTO_ON_ERROR(i2s_std_set_slot(handle, slot_cfg), err, TAG, "set i2s standard slot failed");
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/* If the slot bit width changed, then need to update the clock */
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uint32_t slot_bits = slot_cfg->slot_bit_width == I2S_SLOT_BIT_WIDTH_AUTO ? slot_cfg->data_bit_width : slot_cfg->slot_bit_width;
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if (std_cfg->slot_cfg.slot_bit_width == slot_bits) {
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ESP_GOTO_ON_ERROR(i2s_std_set_clock(handle, &std_cfg->clk_cfg), err, TAG, "update clock failed");
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}
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xSemaphoreGive(handle->mutex);
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return ESP_OK;
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err:
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xSemaphoreGive(handle->mutex);
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return ret;
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}
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esp_err_t i2s_channel_reconfig_std_gpio(i2s_chan_handle_t handle, const i2s_std_gpio_config_t *gpio_cfg)
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{
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I2S_NULL_POINTER_CHECK(TAG, handle);
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I2S_NULL_POINTER_CHECK(TAG, gpio_cfg);
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esp_err_t ret = ESP_OK;
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xSemaphoreTake(handle->mutex, portMAX_DELAY);
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ESP_GOTO_ON_FALSE(handle->mode == I2S_COMM_MODE_STD, ESP_ERR_INVALID_ARG, err, TAG, "This handle is not working in standard moded");
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ESP_GOTO_ON_FALSE(handle->state == I2S_CHAN_STATE_READY, ESP_ERR_INVALID_STATE, err, TAG, "Invalid state, I2S should be disabled before reconfiguring the gpio");
|
|
|
|
ESP_GOTO_ON_ERROR(i2s_std_set_gpio(handle, gpio_cfg), err, TAG, "set i2s standard slot failed");
|
|
xSemaphoreGive(handle->mutex);
|
|
|
|
return ESP_OK;
|
|
err:
|
|
xSemaphoreGive(handle->mutex);
|
|
return ret;
|
|
}
|