kopia lustrzana https://github.com/espressif/esp-idf
459 wiersze
19 KiB
C
459 wiersze
19 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*----------------------------------------------------------------------------------------------------
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* Abstraction layer for PSRAM. PSRAM device related registers and MMU/Cache related code shouls be
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* abstracted to lower layers.
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*
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* When we add more types of external RAM memory, this can be made into a more intelligent dispatcher.
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*----------------------------------------------------------------------------------------------------*/
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "freertos/FreeRTOS.h"
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#include "esp_heap_caps_init.h"
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#include "hal/mmu_hal.h"
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#include "hal/mmu_ll.h"
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#include "hal/cache_ll.h"
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#include "esp_private/esp_psram_io.h"
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#include "esp_private/esp_psram_extram.h"
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#include "esp_private/mmu_psram_flash.h"
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#include "esp_psram_impl.h"
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#include "esp_psram.h"
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#include "esp_private/esp_mmu_map_private.h"
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#include "esp_mmu_map.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/himem.h"
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#include "esp32/rom/cache.h"
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#include "esp_private/esp_cache_esp32_private.h"
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#endif
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/**
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* Two types of PSRAM memory regions for now:
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* - 8bit aligned
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* - 32bit aligned
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*/
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#define PSRAM_MEM_TYPE_NUM 2
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#define PSRAM_MEM_8BIT_ALIGNED 0
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#define PSRAM_MEM_32BIT_ALIGNED 1
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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extern uint8_t _ext_ram_bss_start;
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extern uint8_t _ext_ram_bss_end;
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#endif //#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
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extern uint8_t _ext_ram_noinit_start;
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extern uint8_t _ext_ram_noinit_end;
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#endif //#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
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typedef struct {
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intptr_t vaddr_start;
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intptr_t vaddr_end;
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size_t size; //in bytes
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} psram_mem_t;
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typedef struct {
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bool is_initialised;
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/**
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* @note 1
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* As we can't use heap allocator during this stage, we need to statically declare these regions.
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* Luckily only S2 has two different types of memory regions:
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* - byte-aligned memory
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* - word-aligned memory
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* On the other hand, the type number usually won't be very big
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*
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* On other chips, only one region is needed.
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* So for chips other than S2, size of `regions_to_heap[1]` and `mapped_regions[1]`will always be zero.
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*
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* If in the future, this condition is worse (dbus memory isn't consecutive), we need to delegate this context
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* to chip-specific files, and only keep a (void *) pointer here pointing to those chip-specific contexts
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*/
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psram_mem_t regions_to_heap[PSRAM_MEM_TYPE_NUM]; //memory regions that are available to be added to the heap allocator
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psram_mem_t mapped_regions[PSRAM_MEM_TYPE_NUM]; //mapped memory regions
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} psram_ctx_t;
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static psram_ctx_t s_psram_ctx;
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static const char* TAG = "esp_psram";
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#if CONFIG_IDF_TARGET_ESP32
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//If no function in esp_himem.c is used, this function will be linked into the
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//binary instead of the one in esp_himem.c, automatically making sure no memory
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//is reserved if no himem function is used.
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size_t __attribute__((weak)) esp_himem_reserved_area_size(void)
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{
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return 0;
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}
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static void IRAM_ATTR s_mapping(int v_start, int size)
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{
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//Enable external RAM in MMU
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cache_sram_mmu_set(0, 0, v_start, 0, 32, (size / 1024 / 32));
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//Flush and enable icache for APP CPU
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
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cache_sram_mmu_set(1, 0, v_start, 0, 32, (size / 1024 / 32));
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#endif
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}
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#endif //CONFIG_IDF_TARGET_ESP32
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esp_err_t esp_psram_init(void)
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{
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if (s_psram_ctx.is_initialised) {
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return ESP_ERR_INVALID_STATE;
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}
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esp_err_t ret = ESP_FAIL;
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ret = esp_psram_impl_enable();
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if (ret != ESP_OK) {
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#if CONFIG_SPIRAM_IGNORE_NOTFOUND
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ESP_EARLY_LOGE(TAG, "PSRAM enabled but initialization failed. Bailing out.");
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#endif
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return ret;
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}
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s_psram_ctx.is_initialised = true;
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uint32_t psram_physical_size = 0;
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ret = esp_psram_impl_get_physical_size(&psram_physical_size);
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assert(ret == ESP_OK);
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ESP_EARLY_LOGI(TAG, "Found %dMB PSRAM device", psram_physical_size / (1024 * 1024));
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ESP_EARLY_LOGI(TAG, "Speed: %dMHz", CONFIG_SPIRAM_SPEED);
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in normal (1-core) mode.");
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#else
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ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in low/high (2-core) mode.");
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#endif
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#endif
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uint32_t psram_available_size = 0;
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ret = esp_psram_impl_get_available_size(&psram_available_size);
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assert(ret == ESP_OK);
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__attribute__((unused)) uint32_t total_available_size = psram_available_size;
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/**
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* `start_page` is the psram physical address in MMU page size.
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* MMU page size on ESP32S2 is 64KB
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* e.g.: psram physical address 16 is in page 0
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*
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* Here we plan to copy FLASH instructions to psram physical address 0, which is the No.0 page.
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*/
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__attribute__((unused)) uint32_t start_page = 0;
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA
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uint32_t used_page = 0;
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#endif
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//------------------------------------Copy Flash .text to PSRAM-------------------------------------//
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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ret = mmu_config_psram_text_segment(start_page, total_available_size, &used_page);
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if (ret != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "No enough psram memory for instructon!");
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abort();
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}
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start_page += used_page;
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psram_available_size -= MMU_PAGE_TO_BYTES(used_page);
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ESP_EARLY_LOGV(TAG, "after copy .text, used page is %d, start_page is %d, psram_available_size is %d B", used_page, start_page, psram_available_size);
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#endif //#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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//------------------------------------Copy Flash .rodata to PSRAM-------------------------------------//
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#if CONFIG_SPIRAM_RODATA
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ret = mmu_config_psram_rodata_segment(start_page, total_available_size, &used_page);
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if (ret != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "No enough psram memory for rodata!");
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abort();
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}
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start_page += used_page;
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psram_available_size -= MMU_PAGE_TO_BYTES(used_page);
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ESP_EARLY_LOGV(TAG, "after copy .rodata, used page is %d, start_page is %d, psram_available_size is %d B", used_page, start_page, psram_available_size);
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#endif //#if CONFIG_SPIRAM_RODATA
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//----------------------------------Map the PSRAM physical range to MMU-----------------------------//
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/**
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* @note 2
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* Similarly to @note 1, we expect HW DBUS memory to be consecutive.
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*
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* If situation is worse in the future (memory region isn't consecutive), we need to put these logics into chip-specific files
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*/
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size_t total_mapped_size = 0;
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size_t size_to_map = 0;
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size_t byte_aligned_size = 0;
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ret = esp_mmu_map_get_max_consecutive_free_block_size(MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_8BIT | MMU_MEM_CAP_32BIT, MMU_TARGET_PSRAM0, &byte_aligned_size);
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assert(ret == ESP_OK);
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size_to_map = MIN(byte_aligned_size, psram_available_size);
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const void *v_start_8bit_aligned = NULL;
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ret = esp_mmu_map_reserve_block_with_caps(size_to_map, MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_8BIT | MMU_MEM_CAP_32BIT, MMU_TARGET_PSRAM0, &v_start_8bit_aligned);
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assert(ret == ESP_OK);
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#if CONFIG_IDF_TARGET_ESP32
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s_mapping((int)v_start_8bit_aligned, size_to_map);
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#else
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uint32_t actual_mapped_len = 0;
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#if MMU_LL_MMU_PER_TARGET
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mmu_hal_map_region(1, MMU_TARGET_PSRAM0, (intptr_t)v_start_8bit_aligned, MMU_PAGE_TO_BYTES(start_page), size_to_map, &actual_mapped_len);
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#else
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mmu_hal_map_region(0, MMU_TARGET_PSRAM0, (intptr_t)v_start_8bit_aligned, MMU_PAGE_TO_BYTES(start_page), size_to_map, &actual_mapped_len);
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#endif
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start_page += BYTES_TO_MMU_PAGE(actual_mapped_len);
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ESP_EARLY_LOGV(TAG, "8bit-aligned-region: actual_mapped_len is 0x%x bytes", actual_mapped_len);
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cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, (uint32_t)v_start_8bit_aligned, actual_mapped_len);
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cache_ll_l1_enable_bus(0, bus_mask);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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bus_mask = cache_ll_l1_get_bus(1, (uint32_t)v_start_8bit_aligned, actual_mapped_len);
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cache_ll_l1_enable_bus(1, bus_mask);
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#endif
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#endif //#if CONFIG_IDF_TARGET_ESP32
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s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].size = size_to_map;
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s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_start = (intptr_t)v_start_8bit_aligned;
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s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_end = (intptr_t)v_start_8bit_aligned + size_to_map;
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s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size = size_to_map;
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s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_start = (intptr_t)v_start_8bit_aligned;
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s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_end = (intptr_t)v_start_8bit_aligned + size_to_map;
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ESP_EARLY_LOGV(TAG, "8bit-aligned-range: 0x%x B, starting from: 0x%x", s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].size, v_start_8bit_aligned);
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total_mapped_size += size_to_map;
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#if CONFIG_IDF_TARGET_ESP32S2
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/**
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* On ESP32S2, there are 2 types of DBUS memory:
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* - byte-aligned-memory
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* - word-aligned-memory
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*
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* If byte-aligned-memory isn't enough, we search for word-aligned-memory to do mapping
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*/
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if (total_mapped_size < psram_available_size) {
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size_to_map = psram_available_size - total_mapped_size;
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size_t word_aligned_size = 0;
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ret = esp_mmu_map_get_max_consecutive_free_block_size(MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT, MMU_TARGET_PSRAM0, &word_aligned_size);
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assert(ret == ESP_OK);
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size_to_map = MIN(word_aligned_size, size_to_map);
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const void *v_start_32bit_aligned = NULL;
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ret = esp_mmu_map_reserve_block_with_caps(size_to_map, MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT, MMU_TARGET_PSRAM0, &v_start_32bit_aligned);
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assert(ret == ESP_OK);
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mmu_hal_map_region(0, MMU_TARGET_PSRAM0, (intptr_t)v_start_32bit_aligned, MMU_PAGE_TO_BYTES(start_page), size_to_map, &actual_mapped_len);
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ESP_EARLY_LOGV(TAG, "32bit-aligned-region: actual_mapped_len is 0x%x bytes", actual_mapped_len);
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cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, (uint32_t)v_start_32bit_aligned, actual_mapped_len);
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cache_ll_l1_enable_bus(0, bus_mask);
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s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].size = size_to_map;
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s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_start = (intptr_t)v_start_32bit_aligned;
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s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_end = (intptr_t)v_start_32bit_aligned + size_to_map;
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s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].size = size_to_map;
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s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_start = (intptr_t)v_start_32bit_aligned;
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s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_end = (intptr_t)v_start_32bit_aligned + size_to_map;
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ESP_EARLY_LOGV(TAG, "32bit-aligned-range: 0x%x B, starting from: 0x%x", s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].size, v_start_32bit_aligned);
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total_mapped_size += size_to_map;
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}
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#endif // #if CONFIG_IDF_TARGET_ESP32S2
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if (total_mapped_size < psram_available_size) {
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ESP_EARLY_LOGW(TAG, "Virtual address not enough for PSRAM, map as much as we can. %dMB is mapped", total_mapped_size / 1024 / 1024);
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}
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/*------------------------------------------------------------------------------
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* After mapping, we DON'T care about the PSRAM PHYSICAL ADDRESSS ANYMORE!
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*----------------------------------------------------------------------------*/
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//------------------------------------Configure .bss in PSRAM-------------------------------------//
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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//should never be negative number
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uint32_t ext_bss_size = ((intptr_t)&_ext_ram_bss_end - (intptr_t)&_ext_ram_bss_start);
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ESP_EARLY_LOGV(TAG, "ext_bss_size is %d", ext_bss_size);
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s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_start += ext_bss_size;
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s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size -= ext_bss_size;
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#endif //#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
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uint32_t ext_noinit_size = ((intptr_t)&_ext_ram_noinit_end - (intptr_t)&_ext_ram_noinit_start);
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ESP_EARLY_LOGV(TAG, "ext_noinit_size is %d", ext_noinit_size);
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s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_start += ext_noinit_size;
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s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size -= ext_noinit_size;
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size -= esp_himem_reserved_area_size() - 1;
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#endif
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//will be removed, TODO: IDF-6944
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#if CONFIG_IDF_TARGET_ESP32
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cache_driver_t drv = {
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NULL,
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esp_psram_extram_writeback_cache,
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};
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cache_register_writeback(&drv);
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#endif
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return ESP_OK;
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}
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esp_err_t esp_psram_extram_add_to_heap_allocator(void)
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{
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esp_err_t ret = ESP_FAIL;
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uint32_t byte_aligned_caps[] = {MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT};
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ret = heap_caps_add_region_with_caps(byte_aligned_caps,
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s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_start,
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s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_end);
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if (ret != ESP_OK) {
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return ret;
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}
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if (s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].size) {
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assert(s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_start);
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uint32_t word_aligned_caps[] = {MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_32BIT};
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ret = heap_caps_add_region_with_caps(word_aligned_caps,
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s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_start,
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s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_end);
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if (ret != ESP_OK) {
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return ret;
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}
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}
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ESP_EARLY_LOGI(TAG, "Adding pool of %dK of PSRAM memory to heap allocator",
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(s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size + s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].size) / 1024);
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return ESP_OK;
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}
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bool IRAM_ATTR esp_psram_check_ptr_addr(const void *p)
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{
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if (!s_psram_ctx.is_initialised) {
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return false;
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}
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return ((intptr_t)p >= s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_start && (intptr_t)p < s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_end) ||
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((intptr_t)p >= s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_start && (intptr_t)p < s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_end);
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}
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esp_err_t esp_psram_extram_reserve_dma_pool(size_t size)
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{
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if (size == 0) {
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return ESP_OK; //no-op
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}
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ESP_EARLY_LOGI(TAG, "Reserving pool of %dK of internal memory for DMA/internal allocations", size / 1024);
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/* Pool may be allocated in multiple non-contiguous chunks, depending on available RAM */
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while (size > 0) {
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size_t next_size = heap_caps_get_largest_free_block(MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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next_size = MIN(next_size, size);
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ESP_EARLY_LOGD(TAG, "Allocating block of size %d bytes", next_size);
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uint8_t *dma_heap = heap_caps_malloc(next_size, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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if (!dma_heap || next_size == 0) {
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return ESP_ERR_NO_MEM;
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}
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uint32_t caps[] = {0, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT};
|
|
esp_err_t e = heap_caps_add_region_with_caps(caps, (intptr_t)dma_heap, (intptr_t)dma_heap + next_size - 1);
|
|
if (e != ESP_OK) {
|
|
return e;
|
|
}
|
|
size -= next_size;
|
|
}
|
|
return ESP_OK;
|
|
}
|
|
|
|
bool IRAM_ATTR __attribute__((pure)) esp_psram_is_initialized(void)
|
|
{
|
|
return s_psram_ctx.is_initialised;
|
|
}
|
|
|
|
size_t esp_psram_get_size(void)
|
|
{
|
|
uint32_t available_size = 0;
|
|
esp_err_t ret = esp_psram_impl_get_available_size(&available_size);
|
|
if (ret != ESP_OK) {
|
|
//This means PSRAM isn't initialised, to keep back-compatibility, set size to 0.
|
|
available_size = 0;
|
|
}
|
|
return (size_t)available_size;
|
|
}
|
|
|
|
uint8_t esp_psram_io_get_cs_io(void)
|
|
{
|
|
return esp_psram_impl_get_cs_io();
|
|
}
|
|
|
|
/*
|
|
Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns
|
|
true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
|
|
initialized (in a two-core system) or after the heap allocator has taken ownership of the memory.
|
|
*/
|
|
static bool s_test_psram(intptr_t v_start, size_t size, intptr_t reserved_start, intptr_t reserved_end)
|
|
{
|
|
volatile int *spiram = (volatile int *)v_start;
|
|
size_t p;
|
|
int errct = 0;
|
|
int initial_err = -1;
|
|
for (p = 0; p < (size / sizeof(int)); p += 8) {
|
|
intptr_t addr = (intptr_t)&spiram[p];
|
|
if ((reserved_start <= addr) && (addr < reserved_end)) {
|
|
continue;
|
|
}
|
|
spiram[p] = p ^ 0xAAAAAAAA;
|
|
}
|
|
for (p = 0; p < (size / sizeof(int)); p += 8) {
|
|
intptr_t addr = (intptr_t)&spiram[p];
|
|
if ((reserved_start <= addr) && (addr < reserved_end)) {
|
|
continue;
|
|
}
|
|
if (spiram[p] != (p ^ 0xAAAAAAAA)) {
|
|
errct++;
|
|
if (errct == 1) {
|
|
initial_err = p * 4;
|
|
}
|
|
}
|
|
}
|
|
if (errct) {
|
|
ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, size / 32, initial_err + v_start);
|
|
return false;
|
|
} else {
|
|
ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK");
|
|
return true;
|
|
}
|
|
|
|
}
|
|
|
|
bool esp_psram_extram_test(void)
|
|
{
|
|
bool test_success = false;
|
|
#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
|
|
intptr_t noinit_vstart = (intptr_t)&_ext_ram_noinit_start;
|
|
intptr_t noinit_vend = (intptr_t)&_ext_ram_noinit_end;
|
|
#else
|
|
intptr_t noinit_vstart = 0;
|
|
intptr_t noinit_vend = 0;
|
|
#endif
|
|
test_success = s_test_psram(s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_start,
|
|
s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].size,
|
|
noinit_vstart,
|
|
noinit_vend);
|
|
if (!test_success) {
|
|
return false;
|
|
}
|
|
|
|
if (s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].size) {
|
|
test_success = s_test_psram(s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_start,
|
|
s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].size,
|
|
0,
|
|
0);
|
|
}
|
|
if (!test_success) {
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|