kopia lustrzana https://github.com/espressif/esp-idf
77 wiersze
2.6 KiB
C
77 wiersze
2.6 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp32s2/clk.h"
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#include "esp32s2/ulp.h"
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#include "esp32s2/ulp_riscv.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/sens_reg.h"
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#include "ulp_private.h"
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#include "esp_rom_sys.h"
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esp_err_t ulp_riscv_run(void)
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{
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/* Reset COCPU when power on. */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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esp_rom_delay_us(20);
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CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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/* The coprocessor cpu trap signal doesnt have a stable reset value,
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force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
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/* Disable ULP timer */
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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/* wait for at least 1 RTC_SLOW_CLK cycle */
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esp_rom_delay_us(20);
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/* Select RISC-V as the ULP_TIMER trigger target. */
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CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SEL);
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/* Select ULP-RISC-V to send the DONE signal. */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE_FORCE);
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/* start ULP_TIMER */
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP);
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SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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return ESP_OK;
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}
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esp_err_t ulp_riscv_load_binary(const uint8_t* program_binary, size_t program_size_bytes)
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{
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if (program_binary == NULL) {
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return ESP_ERR_INVALID_ARG;
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}
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if (program_size_bytes > ULP_RESERVE_MEM) {
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return ESP_ERR_INVALID_SIZE;
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}
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uint8_t* base = (uint8_t*) RTC_SLOW_MEM;
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//Start by clearing memory reserved with zeros, this will also will initialize the bss:
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memset(base, 0, ULP_RESERVE_MEM);
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memcpy(base, program_binary, program_size_bytes);
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return ESP_OK;
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}
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