kopia lustrzana https://github.com/espressif/esp-idf
405 wiersze
15 KiB
C
405 wiersze
15 KiB
C
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// The HAL layer for SPI Slave HD
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#include <string.h>
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#include "esp_types.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "sdkconfig.h"
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#include "soc/spi_periph.h"
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#include "soc/lldesc.h"
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#include "hal/spi_slave_hd_hal.h"
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#include "soc/soc_caps.h"
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//This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros.
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#if SOC_GDMA_SUPPORTED
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#include "soc/gdma_struct.h"
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#include "hal/gdma_ll.h"
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#define spi_dma_ll_rx_reset(dev) gdma_ll_rx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL)
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#define spi_dma_ll_tx_reset(dev) gdma_ll_tx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);
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#define spi_dma_ll_rx_enable_burst_data(dev, enable) gdma_ll_rx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_ll_tx_enable_burst_data(dev, enable) gdma_ll_tx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_ll_rx_enable_burst_desc(dev, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_ll_tx_enable_burst_desc(dev, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_ll_enable_out_auto_wrback(dev, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_ll_set_out_eof_generation(dev, enable) gdma_ll_tx_set_eof_mode(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_ll_rx_start(dev, addr) do {\
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gdma_ll_rx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\
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gdma_ll_rx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\
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} while (0)
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#define spi_dma_ll_tx_start(dev, addr) do {\
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gdma_ll_tx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\
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gdma_ll_tx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\
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} while (0)
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#endif
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static void s_spi_slave_hd_hal_dma_init_config(const spi_slave_hd_hal_context_t *hal)
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{
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spi_dma_ll_rx_enable_burst_data(hal->dma_in, 1);
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spi_dma_ll_tx_enable_burst_data(hal->dma_out, 1);
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spi_dma_ll_rx_enable_burst_desc(hal->dma_in, 1);
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spi_dma_ll_tx_enable_burst_desc(hal->dma_out, 1);
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spi_dma_ll_enable_out_auto_wrback(hal->dma_out, 1);
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}
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void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *hal_config)
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{
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spi_dev_t* hw = SPI_LL_GET_HW(hal_config->host_id);
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hal->dev = hw;
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hal->dma_in = hal_config->dma_in;
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hal->dma_out = hal_config->dma_out;
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hal->append_mode = hal_config->append_mode;
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hal->rx_cur_desc = hal->dmadesc_rx;
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hal->tx_cur_desc = hal->dmadesc_tx;
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//Configure slave
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s_spi_slave_hd_hal_dma_init_config(hal);
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spi_ll_slave_hd_init(hw);
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spi_ll_set_addr_bitlen(hw, hal_config->address_bits);
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spi_ll_set_command_bitlen(hw, hal_config->command_bits);
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spi_ll_set_dummy(hw, hal_config->dummy_bits);
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spi_ll_set_rx_lsbfirst(hw, hal_config->rx_lsbfirst);
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spi_ll_set_tx_lsbfirst(hw, hal_config->tx_lsbfirst);
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spi_ll_slave_set_mode(hw, hal_config->mode, (hal_config->dma_chan != 0));
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spi_ll_disable_intr(hw, UINT32_MAX);
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spi_ll_clear_intr(hw, UINT32_MAX);
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if (!hal_config->append_mode) {
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spi_ll_set_intr(hw, SPI_LL_INTR_CMD7 | SPI_LL_INTR_CMD8);
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bool workaround_required = false;
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if (!spi_ll_get_intr(hw, SPI_LL_INTR_CMD7)) {
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hal->intr_not_triggered |= SPI_EV_RECV;
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workaround_required = true;
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}
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if (!spi_ll_get_intr(hw, SPI_LL_INTR_CMD8)) {
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hal->intr_not_triggered |= SPI_EV_SEND;
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workaround_required = true;
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}
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if (workaround_required) {
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//Workaround if the previous interrupts are not writable
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spi_ll_set_intr(hw, SPI_LL_INTR_TRANS_DONE);
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}
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}
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#if CONFIG_IDF_TARGET_ESP32S2
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//Append mode is only supported on ESP32S2 now
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else {
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spi_ll_enable_intr(hw, SPI_LL_INTR_OUT_EOF | SPI_LL_INTR_CMD7);
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}
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#endif
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spi_ll_slave_hd_set_len_cond(hw, SPI_LL_TRANS_LEN_COND_WRBUF |
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SPI_LL_TRANS_LEN_COND_WRDMA |
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SPI_LL_TRANS_LEN_COND_RDBUF |
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SPI_LL_TRANS_LEN_COND_RDDMA);
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spi_ll_slave_set_seg_mode(hal->dev, true);
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}
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uint32_t spi_salve_hd_hal_get_max_bus_size(spi_slave_hd_hal_context_t *hal)
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{
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return hal->dma_desc_num * LLDESC_MAX_NUM_PER_DESC;
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}
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uint32_t spi_slave_hd_hal_get_total_desc_size(spi_slave_hd_hal_context_t *hal, uint32_t bus_size)
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{
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//See how many dma descriptors we need
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int dma_desc_ct = (bus_size + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC;
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if (dma_desc_ct == 0) {
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dma_desc_ct = 1; //default to 4k when max is not given
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}
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hal->dma_desc_num = dma_desc_ct;
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return hal->dma_desc_num * sizeof(spi_slave_hd_hal_desc_append_t);
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}
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void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal, uint8_t *out_buf, size_t len)
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{
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lldesc_setup_link(&hal->dmadesc_rx->desc, out_buf, len, true);
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spi_ll_dma_rx_fifo_reset(hal->dev);
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spi_dma_ll_rx_reset(hal->dma_in);
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spi_ll_slave_reset(hal->dev);
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spi_ll_infifo_full_clr(hal->dev);
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spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD7);
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spi_ll_slave_set_rx_bitlen(hal->dev, len * 8);
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spi_ll_dma_rx_enable(hal->dev, 1);
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spi_dma_ll_rx_start(hal->dma_in, &hal->dmadesc_rx->desc);
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}
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void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len)
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{
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lldesc_setup_link(&hal->dmadesc_tx->desc, data, len, false);
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spi_ll_dma_tx_fifo_reset(hal->dev);
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spi_dma_ll_tx_reset(hal->dma_out);
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spi_ll_slave_reset(hal->dev);
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spi_ll_outfifo_empty_clr(hal->dev);
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spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD8);
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spi_ll_dma_tx_enable(hal->dev, 1);
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spi_dma_ll_tx_start(hal->dma_out, &hal->dmadesc_tx->desc);
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}
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static spi_ll_intr_t get_event_intr(spi_slave_hd_hal_context_t *hal, spi_event_t ev)
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{
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spi_ll_intr_t intr = 0;
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#if CONFIG_IDF_TARGET_ESP32S2
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//Append mode is only supported on ESP32S2 now
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if ((ev & SPI_EV_SEND) && hal->append_mode) intr |= SPI_LL_INTR_OUT_EOF;
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#endif
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if ((ev & SPI_EV_SEND) && !hal->append_mode) intr |= SPI_LL_INTR_CMD8;
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if (ev & SPI_EV_RECV) intr |= SPI_LL_INTR_CMD7;
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if (ev & SPI_EV_BUF_TX) intr |= SPI_LL_INTR_RDBUF;
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if (ev & SPI_EV_BUF_RX) intr |= SPI_LL_INTR_WRBUF;
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if (ev & SPI_EV_CMD9) intr |= SPI_LL_INTR_CMD9;
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if (ev & SPI_EV_CMDA) intr |= SPI_LL_INTR_CMDA;
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if (ev & SPI_EV_TRANS) intr |= SPI_LL_INTR_TRANS_DONE;
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return intr;
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}
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bool spi_slave_hd_hal_check_clear_event(spi_slave_hd_hal_context_t *hal, spi_event_t ev)
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{
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spi_ll_intr_t intr = get_event_intr(hal, ev);
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if (spi_ll_get_intr(hal->dev, intr)) {
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spi_ll_clear_intr(hal->dev, intr);
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return true;
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}
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return false;
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}
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bool spi_slave_hd_hal_check_disable_event(spi_slave_hd_hal_context_t *hal, spi_event_t ev)
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{
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//The trans_done interrupt is used for the workaround when some interrupt is not writable
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spi_ll_intr_t intr = get_event_intr(hal, ev);
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// Workaround for these interrupts not writable
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uint32_t missing_intr = hal->intr_not_triggered & ev;
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if (missing_intr) {
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if ((missing_intr & SPI_EV_RECV) && spi_ll_get_intr(hal->dev, SPI_LL_INTR_CMD7)) {
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hal->intr_not_triggered &= ~SPI_EV_RECV;
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}
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if ((missing_intr & SPI_EV_SEND) && spi_ll_get_intr(hal->dev, SPI_LL_INTR_CMD8)) {
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hal->intr_not_triggered &= ~SPI_EV_SEND;
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}
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if (spi_ll_get_intr(hal->dev, SPI_LL_INTR_TRANS_DONE)) {
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spi_ll_disable_intr(hal->dev, SPI_LL_INTR_TRANS_DONE);
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}
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}
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if (spi_ll_get_intr(hal->dev, intr)) {
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spi_ll_disable_intr(hal->dev, intr);
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return true;
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}
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return false;
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}
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void spi_slave_hd_hal_enable_event_intr(spi_slave_hd_hal_context_t* hal, spi_event_t ev)
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{
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spi_ll_intr_t intr = get_event_intr(hal, ev);
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spi_ll_enable_intr(hal->dev, intr);
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}
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void spi_slave_hd_hal_invoke_event_intr(spi_slave_hd_hal_context_t* hal, spi_event_t ev)
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{
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spi_ll_intr_t intr = get_event_intr(hal, ev);
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// Workaround for these interrupts not writable
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if (hal->intr_not_triggered & ev & (SPI_EV_RECV | SPI_EV_SEND)) {
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intr |= SPI_LL_INTR_TRANS_DONE;
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}
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spi_ll_enable_intr(hal->dev, intr);
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}
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void spi_slave_hd_hal_read_buffer(spi_slave_hd_hal_context_t *hal, int addr, uint8_t *out_data, size_t len)
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{
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spi_ll_read_buffer_byte(hal->dev, addr, out_data, len);
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}
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void spi_slave_hd_hal_write_buffer(spi_slave_hd_hal_context_t *hal, int addr, uint8_t *data, size_t len)
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{
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spi_ll_write_buffer_byte(hal->dev, addr, data, len);
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}
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int spi_slave_hd_hal_get_last_addr(spi_slave_hd_hal_context_t *hal)
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{
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return spi_ll_slave_hd_get_last_addr(hal->dev);
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}
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int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal)
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{
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//this is by -byte
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return spi_ll_slave_get_rx_byte_len(hal->dev);
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}
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int spi_slave_hd_hal_rxdma_seg_get_len(spi_slave_hd_hal_context_t *hal)
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{
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lldesc_t* desc = &hal->dmadesc_rx->desc;
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return lldesc_get_received_len(desc, NULL);
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}
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bool spi_slave_hd_hal_get_tx_finished_trans(spi_slave_hd_hal_context_t *hal, void **out_trans)
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{
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if (!hal->tx_dma_head || hal->tx_dma_head->desc.owner) {
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return false;
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}
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*out_trans = hal->tx_dma_head->arg;
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hal->tx_recycled_desc_cnt++;
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hal->tx_dma_head = (spi_slave_hd_hal_desc_append_t *)STAILQ_NEXT(&hal->tx_dma_head->desc, qe);
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return true;
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}
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bool spi_slave_hd_hal_get_rx_finished_trans(spi_slave_hd_hal_context_t *hal, void **out_trans, size_t *out_len)
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{
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if (!hal->rx_dma_head || hal->rx_dma_head->desc.owner) {
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return false;
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}
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*out_trans = hal->rx_dma_head->arg;
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*out_len = hal->rx_dma_head->desc.length;
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hal->rx_recycled_desc_cnt++;
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hal->rx_dma_head = (spi_slave_hd_hal_desc_append_t *)STAILQ_NEXT(&hal->rx_dma_head->desc, qe);
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return true;
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}
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#if CONFIG_IDF_TARGET_ESP32S2
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//Append mode is only supported on ESP32S2 now
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static void spi_slave_hd_hal_link_append_desc(spi_slave_hd_hal_desc_append_t *dmadesc, const void *data, int len, bool isrx, void *arg)
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{
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assert(len <= LLDESC_MAX_NUM_PER_DESC); //TODO: Add support for transaction with length larger than 4092, IDF-2660
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int n = 0;
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while (len) {
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int dmachunklen = len;
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if (dmachunklen > LLDESC_MAX_NUM_PER_DESC) {
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dmachunklen = LLDESC_MAX_NUM_PER_DESC;
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}
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if (isrx) {
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//Receive needs DMA length rounded to next 32-bit boundary
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dmadesc[n].desc.size = (dmachunklen + 3) & (~3);
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dmadesc[n].desc.length = (dmachunklen + 3) & (~3);
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} else {
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dmadesc[n].desc.size = dmachunklen;
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dmadesc[n].desc.length = dmachunklen;
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}
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dmadesc[n].desc.buf = (uint8_t *)data;
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dmadesc[n].desc.eof = 0;
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dmadesc[n].desc.sosf = 0;
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dmadesc[n].desc.owner = 1;
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dmadesc[n].desc.qe.stqe_next = &dmadesc[n + 1].desc;
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dmadesc[n].arg = arg;
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len -= dmachunklen;
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data += dmachunklen;
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n++;
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}
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dmadesc[n - 1].desc.eof = 1; //Mark last DMA desc as end of stream.
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dmadesc[n - 1].desc.qe.stqe_next = NULL;
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}
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esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len, void *arg)
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{
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//Check if there are enough available DMA descriptors for software to use
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int num_required = (len + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC;
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int not_recycled_desc_num = hal->tx_used_desc_cnt - hal->tx_recycled_desc_cnt;
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int available_desc_num = hal->dma_desc_num - not_recycled_desc_num;
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if (num_required > available_desc_num) {
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return ESP_ERR_INVALID_STATE;
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}
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spi_slave_hd_hal_link_append_desc(hal->tx_cur_desc, data, len, false, arg);
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if (!hal->tx_dma_head) {
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//start a new link
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hal->tx_dma_head = hal->tx_cur_desc;
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hal->tx_dma_tail = hal->tx_cur_desc;
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spi_dma_ll_tx_reset(hal->dma_out);
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spi_ll_outfifo_empty_clr(hal->dev);
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spi_ll_clear_intr(hal->dev, SPI_LL_INTR_OUT_EOF);
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spi_ll_dma_tx_enable(hal->dev, 1);
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spi_dma_ll_tx_start(hal->dma_out, &hal->tx_dma_head->desc);
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} else {
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//there is already a link
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STAILQ_NEXT(&hal->tx_dma_tail->desc, qe) = &hal->tx_cur_desc->desc;
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hal->tx_dma_tail = hal->tx_cur_desc;
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spi_dma_ll_tx_restart(hal->dma_out);
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}
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//Move the current descriptor pointer according to the number of the linked descriptors
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for (int i = 0; i < num_required; i++) {
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hal->tx_used_desc_cnt++;
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hal->tx_cur_desc++;
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if (hal->tx_cur_desc == hal->dmadesc_tx + hal->dma_desc_num) {
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hal->tx_cur_desc = hal->dmadesc_tx;
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}
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}
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return ESP_OK;
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}
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esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len, void *arg)
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{
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//Check if there are enough available dma descriptors for software to use
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int num_required = (len + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC;
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int not_recycled_desc_num = hal->rx_used_desc_cnt - hal->rx_recycled_desc_cnt;
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int available_desc_num = hal->dma_desc_num - not_recycled_desc_num;
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if (num_required > available_desc_num) {
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return ESP_ERR_INVALID_STATE;
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}
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spi_slave_hd_hal_link_append_desc(hal->rx_cur_desc, data, len, false, arg);
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if (!hal->rx_dma_head) {
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//start a new link
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hal->rx_dma_head = hal->rx_cur_desc;
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hal->rx_dma_tail = hal->rx_cur_desc;
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spi_dma_ll_rx_reset(hal->dma_in);
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spi_ll_infifo_full_clr(hal->dev);
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spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD7);
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spi_ll_dma_rx_enable(hal->dev, 1);
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spi_dma_ll_rx_start(hal->dma_in, &hal->rx_dma_head->desc);
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} else {
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//there is already a link
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STAILQ_NEXT(&hal->rx_dma_tail->desc, qe) = &hal->rx_cur_desc->desc;
|
|
hal->rx_dma_tail = hal->rx_cur_desc;
|
|
|
|
spi_dma_ll_rx_restart(hal->dma_in);
|
|
}
|
|
|
|
//Move the current descriptor pointer according to the number of the linked descriptors
|
|
for (int i = 0; i < num_required; i++) {
|
|
hal->rx_used_desc_cnt++;
|
|
hal->rx_cur_desc++;
|
|
if (hal->rx_cur_desc == hal->dmadesc_rx + hal->dma_desc_num) {
|
|
hal->rx_cur_desc = hal->dmadesc_rx;
|
|
}
|
|
}
|
|
|
|
return ESP_OK;
|
|
}
|
|
#endif //#if CONFIG_IDF_TARGET_ESP32S2
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