esp-idf/components/riscv
Marius Vikhammer be839733ed fix(interrupt): fixed exit critical section on P4/C5
When adjusting the interrupt level treshold on P4/C6 during a critical section exit
it would take a few cycles before this is taken into account by the CPU.

This meant that under some circumstances, e.g. 02, we could do
yield()->vPortExitCritical()->vPortEnterCritical()
without getting rescheduled.
This causes issues for freertos as it assumes the task will not continue into the
vPortEnterCritical before the scheduler has schedulded it again.

This meant that e.g. xTaskNotifyWait would yield, but then immeditaly continue as if
it was already notified.
2024-03-24 13:13:42 +08:00
..
include fix(interrupt): fixed exit critical section on P4/C5 2024-03-24 13:13:42 +08:00
ld refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
CMakeLists.txt refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
instruction_decode.c refactor(tools): Tidy up core component files copyright ignore 2024-01-22 18:07:35 +08:00
interrupt.c feat(esp32c61): add G0 component support 2024-03-18 14:28:27 +08:00
interrupt_clic.c refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
interrupt_intc.c refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
interrupt_plic.c refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
linker.lf
project_include.cmake
vectors.S refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
vectors_clic.S feat(system): esp32p4: support hw stack guard 2024-03-21 14:30:21 +04:00
vectors_intc.S