kopia lustrzana https://github.com/espressif/esp-idf
99 wiersze
3.0 KiB
C
99 wiersze
3.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include <sys/param.h>
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#include "soc/soc_caps.h"
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#include "hal/assert.h"
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#include "hal/efuse_hal.h"
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#include "hal/efuse_ll.h"
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#include "esp_attr.h"
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#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x08 << (4 * (block))))
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#define ESP_EFUSE_BLOCK_ERROR_NUM_BITS(error_reg, block) ((error_reg) & (0x07 << (4 * (block))))
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IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
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{
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return efuse_ll_get_chip_wafer_version_major();
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}
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IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
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{
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return efuse_ll_get_chip_wafer_version_minor();
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}
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/******************* eFuse control functions *************************/
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void efuse_hal_set_timing(uint32_t apb_freq_hz)
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{
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(void) apb_freq_hz;
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efuse_ll_set_dac_num(0xFF);
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efuse_ll_set_dac_clk_div(0x28);
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efuse_ll_set_pwr_on_num(0x3000);
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efuse_ll_set_pwr_off_num(0x190);
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}
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void efuse_hal_read(void)
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{
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efuse_hal_set_timing(0);
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efuse_ll_set_conf_read_op_code();
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efuse_ll_set_read_cmd();
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while (efuse_ll_get_read_cmd() != 0) { }
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/*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
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while (efuse_ll_get_read_cmd() != 0) { }
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}
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void efuse_hal_clear_program_registers(void)
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{
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ets_efuse_clear_program_registers();
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}
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void efuse_hal_program(uint32_t block)
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{
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efuse_hal_set_timing(0);
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efuse_ll_set_conf_write_op_code();
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efuse_ll_set_pgm_cmd(block);
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while (efuse_ll_get_pgm_cmd() != 0) { }
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efuse_hal_clear_program_registers();
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efuse_hal_read();
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}
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void efuse_hal_rs_calculate(const void *data, void *rs_values)
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{
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ets_efuse_rs_calculate(data, rs_values);
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}
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/******************* eFuse control functions *************************/
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bool efuse_hal_is_coding_error_in_block(unsigned block)
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{
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if (block == 0) {
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for (unsigned i = 0; i < 5; i++) {
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if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) {
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return true;
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}
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}
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} else if (block <= 10) {
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// The order of error in these regs is different only for the C3 chip.
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// Fail bit (mask=0x8):
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// EFUSE_RD_RS_ERR0_REG: (hi) BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1, ------ (low)
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// EFUSE_RD_RS_ERR1_REG: BLOCK9, BLOCK8
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// Error num bits (mask=0x7):
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// EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
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// EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
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// BLOCK10 is not presented in the error regs.
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uint32_t err_fail_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
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uint32_t err_num_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + ((block - 1) / 8) * 4);
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return (ESP_EFUSE_BLOCK_ERROR_BITS(err_fail_reg, block % 8) != 0) || (ESP_EFUSE_BLOCK_ERROR_NUM_BITS(err_num_reg, (block - 1) % 8) != 0);
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}
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return false;
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}
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