kopia lustrzana https://github.com/espressif/esp-idf
80 wiersze
2.7 KiB
C
80 wiersze
2.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_types.h"
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#include "esp_log.h"
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#include "soc/soc_caps.h"
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#include "mspi_timing_config.h"
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#if SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY
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#include "mspi_timing_tuning_configs.h"
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#include "hal/mspi_timing_tuning_ll.h"
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#endif
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#if SOC_MEMSPI_CORE_CLK_SHARED_WITH_PSRAM
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#define FLASH_LOW_SPEED_CORE_CLOCK_MHZ MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT
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#define FLASH_HIGH_SPEED_CORE_CLOCK_MHZ MSPI_TIMING_CORE_CLOCK_MHZ
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#define PSRAM_LOW_SPEED_CORE_CLOCK_MHZ MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT
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#define PSRAM_HIGH_SPEED_CORE_CLOCK_MHZ MSPI_TIMING_CORE_CLOCK_MHZ
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#endif //SOC_MEMSPI_CORE_CLK_SHARED_WITH_PSRAM
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#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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/**
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* Currently we only need these on chips with timing tuning
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*/
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//-------------------------------------MSPI Clock Setting-------------------------------------//
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static void s_mspi_flash_set_core_clock(uint8_t spi_num, uint32_t core_clock_mhz)
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{
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mspi_timing_ll_set_core_clock(spi_num, core_clock_mhz);
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}
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static void s_mspi_psram_set_core_clock(uint8_t spi_num, uint32_t core_clock_mhz)
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{
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mspi_timing_ll_set_core_clock(spi_num, core_clock_mhz);
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}
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void mspi_timing_config_set_flash_clock(uint32_t flash_freq_mhz, mspi_timing_speed_mode_t speed_mode, bool control_both_mspi)
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{
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uint32_t core_clock_mhz = 0;
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if (speed_mode == MSPI_TIMING_SPEED_MODE_LOW_PERF) {
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core_clock_mhz = FLASH_LOW_SPEED_CORE_CLOCK_MHZ;
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} else {
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core_clock_mhz = FLASH_HIGH_SPEED_CORE_CLOCK_MHZ;
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}
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//SPI0 and SPI1 share the register for core clock. So we only set SPI0 here.
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s_mspi_flash_set_core_clock(0, core_clock_mhz);
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uint32_t freqdiv = core_clock_mhz / flash_freq_mhz;
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assert(freqdiv > 0);
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mspi_timing_ll_set_flash_clock(0, freqdiv);
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if (control_both_mspi) {
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mspi_timing_ll_set_flash_clock(1, freqdiv);
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}
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}
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void mspi_timing_config_set_psram_clock(uint32_t psram_freq_mhz, mspi_timing_speed_mode_t speed_mode, bool control_both_mspi)
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{
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(void)control_both_mspi; // for compatibility
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uint32_t core_clock_mhz = 0;
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if (speed_mode == MSPI_TIMING_SPEED_MODE_LOW_PERF) {
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core_clock_mhz = PSRAM_LOW_SPEED_CORE_CLOCK_MHZ;
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} else {
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core_clock_mhz = PSRAM_HIGH_SPEED_CORE_CLOCK_MHZ;
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}
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//SPI0 and SPI1 share the register for core clock. So we only set SPI0 here.
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s_mspi_psram_set_core_clock(0, core_clock_mhz);
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uint32_t freqdiv = core_clock_mhz / psram_freq_mhz;
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assert(freqdiv > 0);
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mspi_timing_ll_set_psram_clock(0, freqdiv);
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}
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#endif //#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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