kopia lustrzana https://github.com/espressif/esp-idf
496 wiersze
17 KiB
C
496 wiersze
17 KiB
C
#include <stdio.h>
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#include <stdlib.h>
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#include "xtensa/core-macros.h"
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#include "xtensa/hal.h"
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#include "esp_types.h"
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#include "esp32/clk.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/xtensa_timer.h"
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#include "soc/cpu.h"
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#include "unity.h"
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#include "test_utils.h"
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#include "esp_rom_uart.h"
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#include "hal/uart_types.h"
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#include "hal/uart_ll.h"
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#include "soc/dport_reg.h"
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#include "soc/rtc.h"
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#include "esp_intr_alloc.h"
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#include "driver/timer.h"
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#define MHZ (1000000)
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static volatile bool exit_flag;
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static bool dport_test_result;
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static bool apb_test_result;
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uint32_t volatile apb_intr_test_result;
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static void accessDPORT(void *pvParameters)
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{
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xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
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uint32_t dport_date = DPORT_REG_READ(DPORT_DATE_REG);
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dport_test_result = true;
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// although exit flag is set in another task, checking (exit_flag == false) is safe
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while (exit_flag == false) {
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if (dport_date != DPORT_REG_READ(DPORT_DATE_REG)) {
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dport_test_result = false;
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break;
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}
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}
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xSemaphoreGive(*sema);
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vTaskDelete(NULL);
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}
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static void accessAPB(void *pvParameters)
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{
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xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
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uint32_t uart_date = REG_READ(UART_DATE_REG(0));
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apb_test_result = true;
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// although exit flag is set in another task, checking (exit_flag == false) is safe
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while (exit_flag == false) {
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if (uart_date != REG_READ(UART_DATE_REG(0))) {
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apb_test_result = false;
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break;
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}
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}
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xSemaphoreGive(*sema);
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vTaskDelete(NULL);
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}
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void run_tasks(const char *task1_description, void (* task1_func)(void *), const char *task2_description, void (* task2_func)(void *), uint32_t delay_ms)
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{
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apb_intr_test_result = 1;
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int i;
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TaskHandle_t th[2];
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xSemaphoreHandle exit_sema[2];
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for (i=0; i<2; i++) {
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if((task1_func != NULL && i == 0) || (task2_func != NULL && i == 1)){
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exit_sema[i] = xSemaphoreCreateBinary();
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}
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}
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exit_flag = false;
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#ifndef CONFIG_FREERTOS_UNICORE
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printf("assign task accessing DPORT to core 0 and task accessing APB to core 1\n");
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if(task1_func != NULL) xTaskCreatePinnedToCore(task1_func, task1_description, 2048, &exit_sema[0], UNITY_FREERTOS_PRIORITY - 1, &th[0], 0);
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if(task2_func != NULL) xTaskCreatePinnedToCore(task2_func, task2_description, 2048, &exit_sema[1], UNITY_FREERTOS_PRIORITY - 1, &th[1], 1);
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#else
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printf("assign task accessing DPORT and accessing APB\n");
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if(task1_func != NULL) xTaskCreate(task1_func, task1_description, 2048, &exit_sema[0], UNITY_FREERTOS_PRIORITY - 1, &th[0]);
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if(task2_func != NULL) xTaskCreate(task2_func, task2_description, 2048, &exit_sema[1], UNITY_FREERTOS_PRIORITY - 1, &th[1]);
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#endif
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printf("start wait for %d seconds [Test %s and %s]\n", delay_ms/1000, task1_description, task2_description);
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vTaskDelay(delay_ms / portTICK_PERIOD_MS);
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// set exit flag to let thread exit
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exit_flag = true;
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for (i=0; i<2; i++) {
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if ((task1_func != NULL && i == 0) || (task2_func != NULL && i == 1)) {
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xSemaphoreTake(exit_sema[i], portMAX_DELAY);
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vSemaphoreDelete(exit_sema[i]);
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}
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}
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TEST_ASSERT(dport_test_result == true && apb_test_result == true && apb_intr_test_result == 1);
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}
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TEST_CASE("access DPORT and APB at same time", "[esp32]")
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{
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dport_test_result = false;
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apb_test_result = false;
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printf("CPU_FREQ = %d MHz\n", esp_clk_cpu_freq());
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run_tasks("accessDPORT", accessDPORT, "accessAPB", accessAPB, 10000);
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}
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void run_tasks_with_change_freq_cpu(int cpu_freq_mhz)
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{
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const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
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const int uart_baud = CONFIG_ESP_CONSOLE_UART_BAUDRATE;
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dport_test_result = false;
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apb_test_result = false;
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rtc_cpu_freq_config_t old_config;
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rtc_clk_cpu_freq_get_config(&old_config);
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printf("CPU_FREQ = %d MHz\n", old_config.freq_mhz);
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if (cpu_freq_mhz != old_config.freq_mhz) {
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rtc_cpu_freq_config_t new_config;
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bool res = rtc_clk_cpu_freq_mhz_to_config(cpu_freq_mhz, &new_config);
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assert(res && "invalid frequency value");
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esp_rom_uart_tx_wait_idle(uart_num);
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rtc_clk_cpu_freq_set_config(&new_config);
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uart_ll_set_baudrate(UART_LL_GET_HW(uart_num), UART_SCLK_APB, uart_baud);
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/* adjust RTOS ticks */
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_xt_tick_divisor = cpu_freq_mhz * 1000000 / XT_TICK_PER_SEC;
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vTaskDelay(2);
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printf("CPU_FREQ switched to %d MHz\n", cpu_freq_mhz);
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}
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run_tasks("accessDPORT", accessDPORT, "accessAPB", accessAPB, 10000);
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// return old freq.
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esp_rom_uart_tx_wait_idle(uart_num);
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rtc_clk_cpu_freq_set_config(&old_config);
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uart_ll_set_baudrate(UART_LL_GET_HW(uart_num), UART_SCLK_APB, uart_baud);
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_xt_tick_divisor = old_config.freq_mhz * 1000000 / XT_TICK_PER_SEC;
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}
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TEST_CASE("access DPORT and APB at same time (Freq CPU and APB = 80 MHz)", "[esp32] [ignore]")
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{
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run_tasks_with_change_freq_cpu(80);
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}
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TEST_CASE("access DPORT and APB at same time (Freq CPU and APB = 40 MHz (XTAL))", "[esp32]")
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{
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run_tasks_with_change_freq_cpu((int) rtc_clk_xtal_freq_get());
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}
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static uint32_t stall_other_cpu_counter;
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static uint32_t pre_reading_apb_counter;
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static uint32_t apb_counter;
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static void accessDPORT_stall_other_cpu(void *pvParameters)
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{
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xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
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uint32_t dport_date = DPORT_REG_READ(DPORT_DATE_REG);
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uint32_t dport_date_cur;
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dport_test_result = true;
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stall_other_cpu_counter = 0;
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// although exit flag is set in another task, checking (exit_flag == false) is safe
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while (exit_flag == false) {
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++stall_other_cpu_counter;
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DPORT_STALL_OTHER_CPU_START();
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dport_date_cur = _DPORT_REG_READ(DPORT_DATE_REG);
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DPORT_STALL_OTHER_CPU_END();
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if (dport_date != dport_date_cur) {
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apb_test_result = false;
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break;
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}
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}
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xSemaphoreGive(*sema);
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vTaskDelete(NULL);
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}
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static void accessAPB_measure_performance(void *pvParameters)
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{
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xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
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uint32_t uart_date = REG_READ(UART_DATE_REG(0));
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apb_test_result = true;
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apb_counter = 0;
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// although exit flag is set in another task, checking (exit_flag == false) is safe
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while (exit_flag == false) {
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++apb_counter;
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if (uart_date != REG_READ(UART_DATE_REG(0))) {
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apb_test_result = false;
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break;
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}
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}
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xSemaphoreGive(*sema);
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vTaskDelete(NULL);
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}
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static void accessDPORT_pre_reading_apb(void *pvParameters)
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{
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xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
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uint32_t dport_date = DPORT_REG_READ(DPORT_DATE_REG);
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uint32_t dport_date_cur;
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dport_test_result = true;
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pre_reading_apb_counter = 0;
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// although exit flag is set in another task, checking (exit_flag == false) is safe
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while (exit_flag == false) {
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++pre_reading_apb_counter;
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dport_date_cur = DPORT_REG_READ(DPORT_DATE_REG);
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if (dport_date != dport_date_cur) {
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apb_test_result = false;
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break;
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}
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}
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xSemaphoreGive(*sema);
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vTaskDelete(NULL);
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}
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TEST_CASE("test for DPORT access performance", "[esp32]")
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{
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dport_test_result = true;
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apb_test_result = true;
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typedef struct {
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uint32_t dport;
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uint32_t apb;
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uint32_t summ;
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} test_performance_t;
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test_performance_t t[5] = {0};
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uint32_t delay_ms = 5000;
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run_tasks("-", NULL, "accessAPB", accessAPB_measure_performance, delay_ms);
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t[0].apb = apb_counter;
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t[0].dport = 0;
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t[0].summ = t[0].apb + t[0].dport;
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run_tasks("accessDPORT_stall_other_cpu", accessDPORT_stall_other_cpu, "-", NULL, delay_ms);
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t[1].apb = 0;
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t[1].dport = stall_other_cpu_counter;
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t[1].summ = t[1].apb + t[1].dport;
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run_tasks("accessDPORT_pre_reading_apb", accessDPORT_pre_reading_apb, "-", NULL, delay_ms);
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t[2].apb = 0;
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t[2].dport = pre_reading_apb_counter;
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t[2].summ = t[2].apb + t[2].dport;
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run_tasks("accessDPORT_stall_other_cpu", accessDPORT_stall_other_cpu, "accessAPB", accessAPB_measure_performance, delay_ms);
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t[3].apb = apb_counter;
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t[3].dport = stall_other_cpu_counter;
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t[3].summ = t[3].apb + t[3].dport;
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run_tasks("accessDPORT_pre_reading_apb", accessDPORT_pre_reading_apb, "accessAPB", accessAPB_measure_performance, delay_ms);
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t[4].apb = apb_counter;
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t[4].dport = pre_reading_apb_counter;
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t[4].summ = t[4].apb + t[4].dport;
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printf("\nPerformance table: \n"
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"The number of simultaneous read operations of the APB and DPORT registers\n"
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"by different methods for %d seconds.\n", delay_ms/1000);
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printf("+-----------------------+----------+----------+----------+\n");
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printf("| Method read DPORT | DPORT | APB | SUMM |\n");
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printf("+-----------------------+----------+----------+----------+\n");
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printf("|1.Only accessAPB |%10d|%10d|%10d|\n", t[0].dport, t[0].apb, t[0].summ);
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printf("|2.Only STALL_OTHER_CPU |%10d|%10d|%10d|\n", t[1].dport, t[1].apb, t[1].summ);
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printf("|3.Only PRE_READ_APB_REG|%10d|%10d|%10d|\n", t[2].dport, t[2].apb, t[2].summ);
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printf("+-----------------------+----------+----------+----------+\n");
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printf("|4.STALL_OTHER_CPU |%10d|%10d|%10d|\n", t[3].dport, t[3].apb, t[3].summ);
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printf("|5.PRE_READ_APB_REG |%10d|%10d|%10d|\n", t[4].dport, t[4].apb, t[4].summ);
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printf("+-----------------------+----------+----------+----------+\n");
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printf("| ratio=PRE_READ/STALL |%10f|%10f|%10f|\n", (float)t[4].dport/t[3].dport, (float)t[4].apb/t[3].apb, (float)t[4].summ/t[3].summ);
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printf("+-----------------------+----------+----------+----------+\n");
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}
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#define REPEAT_OPS 10000
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static uint32_t start, end;
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#define BENCHMARK_START() do { \
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RSR(CCOUNT, start); \
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} while(0)
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#define BENCHMARK_END(OPERATION) do { \
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RSR(CCOUNT, end); \
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printf("%s took %d cycles/op (%d cycles for %d ops)\n", \
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OPERATION, (end - start)/REPEAT_OPS, \
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(end - start), REPEAT_OPS); \
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} while(0)
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TEST_CASE("BENCHMARK for DPORT access performance", "[freertos]")
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{
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BENCHMARK_START();
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for (int i = 0; i < REPEAT_OPS; i++) {
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DPORT_STALL_OTHER_CPU_START();
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_DPORT_REG_READ(DPORT_DATE_REG);
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DPORT_STALL_OTHER_CPU_END();
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}
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BENCHMARK_END("[old]DPORT access STALL OTHER CPU");
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BENCHMARK_START();
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for (int i = 0; i < REPEAT_OPS; i++) {
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DPORT_REG_READ(DPORT_DATE_REG);
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}
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BENCHMARK_END("[new]DPORT access PRE-READ APB REG");
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BENCHMARK_START();
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for (int i = 0; i < REPEAT_OPS; i++) {
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DPORT_SEQUENCE_REG_READ(DPORT_DATE_REG);
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}
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BENCHMARK_END("[seq]DPORT access PRE-READ APB REG");
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BENCHMARK_START();
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for (int i = 0; i < REPEAT_OPS; i++) {
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REG_READ(UART_DATE_REG(0));
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}
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BENCHMARK_END("REG_READ");
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BENCHMARK_START();
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for (int i = 0; i < REPEAT_OPS; i++) {
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_DPORT_REG_READ(DPORT_DATE_REG);
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}
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BENCHMARK_END("_DPORT_REG_READ");
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}
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uint32_t xt_highint5_read_apb;
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#ifndef CONFIG_FREERTOS_UNICORE
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timer_isr_handle_t inth;
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xSemaphoreHandle sync_sema;
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static void init_hi_interrupt(void *arg)
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{
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printf("init hi_interrupt on CPU%d \n", xPortGetCoreID());
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TEST_ESP_OK(esp_intr_alloc(ETS_INTERNAL_TIMER2_INTR_SOURCE, ESP_INTR_FLAG_LEVEL5 | ESP_INTR_FLAG_IRAM, NULL, NULL, &inth));
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while (exit_flag == false);
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esp_intr_free(inth);
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printf("disable hi_interrupt on CPU%d \n", xPortGetCoreID());
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vTaskDelete(NULL);
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}
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static void accessDPORT2_stall_other_cpu(void *pvParameters)
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{
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xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
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dport_test_result = true;
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while (exit_flag == false) {
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DPORT_STALL_OTHER_CPU_START();
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XTHAL_SET_CCOMPARE(2, XTHAL_GET_CCOUNT());
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xt_highint5_read_apb = 1;
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for (int i = 0; i < 200; ++i) {
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if (_DPORT_REG_READ(DPORT_DATE_REG) != _DPORT_REG_READ(DPORT_DATE_REG)) {
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apb_test_result = false;
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break;
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}
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}
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xt_highint5_read_apb = 0;
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DPORT_STALL_OTHER_CPU_END();
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}
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printf("accessDPORT2_stall_other_cpu finish\n");
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xSemaphoreGive(*sema);
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vTaskDelete(NULL);
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}
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TEST_CASE("Check stall workaround DPORT and Hi-interrupt", "[esp32]")
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{
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xt_highint5_read_apb = 0;
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dport_test_result = false;
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apb_test_result = true;
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TEST_ASSERT(xTaskCreatePinnedToCore(&init_hi_interrupt, "init_hi_intr", 2048, NULL, 6, NULL, 1) == pdTRUE);
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// Access DPORT(stall other cpu method) - CPU0
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// STALL - CPU1
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// Hi-interrupt - CPU1
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run_tasks("accessDPORT2_stall_other_cpu", accessDPORT2_stall_other_cpu, " - ", NULL, 10000);
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}
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static void accessDPORT2(void *pvParameters)
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{
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xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
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dport_test_result = true;
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TEST_ESP_OK(esp_intr_alloc(ETS_INTERNAL_TIMER2_INTR_SOURCE, ESP_INTR_FLAG_LEVEL5 | ESP_INTR_FLAG_IRAM, NULL, NULL, &inth));
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while (exit_flag == false) {
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XTHAL_SET_CCOMPARE(2, XTHAL_GET_CCOUNT() + 21);
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for (int i = 0; i < 200; ++i) {
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if (DPORT_REG_READ(DPORT_DATE_REG) != DPORT_REG_READ(DPORT_DATE_REG)) {
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dport_test_result = false;
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break;
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}
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}
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}
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esp_intr_free(inth);
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printf("accessDPORT2 finish\n");
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xSemaphoreGive(*sema);
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vTaskDelete(NULL);
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}
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TEST_CASE("Check pre-read workaround DPORT and Hi-interrupt", "[esp32]")
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{
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xt_highint5_read_apb = 0;
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dport_test_result = false;
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apb_test_result = true;
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// Access DPORT(pre-read method) - CPU1
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// Hi-interrupt - CPU1
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run_tasks("accessAPB", accessAPB, "accessDPORT2", accessDPORT2, 10000);
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}
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static uint32_t s_shift_counter;
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/*
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The test_dport_access_reg_read() is similar DPORT_REG_READ() but has differents:
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- generate an interrupt by SET_CCOMPARE
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- additional branch command helps get good reproducing an issue with breaking the DPORT pre-read workaround
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- uncomment (1) and comment (2) it allows seeing the broken pre-read workaround
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For pre-reading the workaround, it is important that the two reading commands APB and DPORT
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are executed without interruption. For this reason, it disables interrupts and to do reading inside the safe area.
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But despite a disabling interrupt it was still possible that these two readings can be interrupted.
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The reason is linked with work parallel execution commands in the pipeline (it is not a bug).
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To resolve this issue (1) was moved to (2) position into the disabled interrupt part.
|
|
When the read command is interrupted after stage E(execute), the result of its execution will be saved in the internal buffer,
|
|
and after returning from the interrupt, this command takes this value from the buffer without repeating the reading,
|
|
which is critical for the DPORT pre-read workaround. To fix it we added additional command under safe area ((1)->(2)).
|
|
*/
|
|
static uint32_t IRAM_ATTR test_dport_access_reg_read(uint32_t reg)
|
|
{
|
|
#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
|
|
return _DPORT_REG_READ(reg);
|
|
#else
|
|
uint32_t apb;
|
|
unsigned int intLvl;
|
|
XTHAL_SET_CCOMPARE(2, XTHAL_GET_CCOUNT() + s_shift_counter);
|
|
__asm__ __volatile__ (\
|
|
/* "movi %[APB], "XTSTR(0x3ff40078)"\n" */ /* (1) uncomment for reproduce issue */ \
|
|
"bnez %[APB], kl1\n" /* this branch command helps get good reproducing */ \
|
|
"kl1:\n"\
|
|
"rsil %[LVL], "XTSTR(CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL)"\n"\
|
|
"movi %[APB], "XTSTR(0x3ff40078)"\n" /* (2) comment for reproduce issue */ \
|
|
"l32i %[APB], %[APB], 0\n"\
|
|
"l32i %[REG], %[REG], 0\n"\
|
|
"wsr %[LVL], "XTSTR(PS)"\n"\
|
|
"rsync\n"\
|
|
: [APB]"=a"(apb), [REG]"+a"(reg), [LVL]"=a"(intLvl)\
|
|
: \
|
|
: "memory" \
|
|
);
|
|
return reg;
|
|
#endif
|
|
}
|
|
|
|
// The accessDPORT3 task is similar accessDPORT2 but uses test_dport_access_reg_read() instead of usual DPORT_REG_READ().
|
|
static void accessDPORT3(void *pvParameters)
|
|
{
|
|
xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
|
|
dport_test_result = true;
|
|
|
|
TEST_ESP_OK(esp_intr_alloc(ETS_INTERNAL_TIMER2_INTR_SOURCE, ESP_INTR_FLAG_LEVEL5 | ESP_INTR_FLAG_IRAM, NULL, NULL, &inth));
|
|
int i = 0;
|
|
while (exit_flag == false) {
|
|
if (test_dport_access_reg_read(DPORT_DATE_REG) != test_dport_access_reg_read(DPORT_DATE_REG)) {
|
|
dport_test_result = false;
|
|
break;
|
|
}
|
|
if ((++i % 100) == 0) {
|
|
s_shift_counter = (s_shift_counter + 1) % 30;
|
|
}
|
|
}
|
|
esp_intr_free(inth);
|
|
printf("accessDPORT3 finish\n");
|
|
|
|
xSemaphoreGive(*sema);
|
|
vTaskDelete(NULL);
|
|
}
|
|
|
|
TEST_CASE("Check pre-read workaround DPORT and Hi-interrupt (2)", "[esp32]")
|
|
{
|
|
s_shift_counter = 1;
|
|
xt_highint5_read_apb = 0;
|
|
dport_test_result = false;
|
|
apb_test_result = true;
|
|
// Access DPORT(pre-read method) - CPU1
|
|
// Hi-interrupt - CPU1
|
|
run_tasks("accessAPB", accessAPB, "accessDPORT3", accessDPORT3, 10000);
|
|
}
|
|
#endif // CONFIG_FREERTOS_UNICORE
|