kopia lustrzana https://github.com/espressif/esp-idf
142 wiersze
4.0 KiB
C
142 wiersze
4.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <sys/param.h>
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#include "esp_spi_flash.h"
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#include "soc/system_reg.h"
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#include "soc/soc_memory_layout.h"
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#include "esp32h2/rom/cache.h"
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#include "hal/spi_flash_hal.h"
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#include "esp_flash.h"
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#include "esp_log.h"
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#include "esp_attr.h"
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#include "esp_rom_spiflash.h"
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static const char *TAG = "spiflash_h2";
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#define SPICACHE SPIMEM0
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#define SPIFLASH SPIMEM1
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extern void IRAM_ATTR flash_rom_init(void);
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esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_addr, const void *src, size_t size)
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{
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const spi_flash_guard_funcs_t *ops = spi_flash_guard_get();
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esp_rom_spiflash_result_t rc;
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assert((dest_addr % 16) == 0);
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assert((size % 16) == 0);
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/* src needs to be 32 bit aligned */
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if (!esp_ptr_internal(src) || (intptr_t)src & 0x3) {
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WORD_ALIGNED_ATTR uint8_t block[128]; // Need to buffer in RAM as we write
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while (size > 0) {
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size_t next_block = MIN(size, sizeof(block));
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memcpy(block, src, next_block);
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esp_rom_spiflash_result_t r = spi_flash_write_encrypted_chip(dest_addr, block, next_block);
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if (r != ESP_ROM_SPIFLASH_RESULT_OK) {
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return r;
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}
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size -= next_block;
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dest_addr += next_block;
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src = ((uint8_t *)src) + next_block;
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}
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bzero(block, sizeof(block));
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return ESP_ROM_SPIFLASH_RESULT_OK;
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} else { // Already in internal memory
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ESP_LOGV(TAG, "calling esp_rom_spiflash_write_encrypted addr 0x%x src %p size 0x%x", dest_addr, src, size);
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#ifndef CONFIG_SPI_FLASH_USE_LEGACY_IMPL
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/* The ROM function SPI_Encrypt_Write assumes ADDR_BITLEN is already set but new
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implementation doesn't automatically set this to a usable value */
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SPIFLASH.user1.usr_addr_bitlen = 23;
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#endif
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if (ops && ops->start) {
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ops->start();
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}
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flash_rom_init();
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rc = esp_rom_spiflash_write_encrypted(dest_addr, (uint32_t *)src, size);
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if (ops && ops->end) {
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ops->end();
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}
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return rc;
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}
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}
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#define FLASH_WRAP_CMD 0x77
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esp_err_t spi_flash_wrap_set(spi_flash_wrap_mode_t mode)
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{
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uint32_t reg_bkp_ctrl = SPIFLASH.ctrl.val;
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uint32_t reg_bkp_usr = SPIFLASH.user.val;
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SPIFLASH.user.fwrite_dio = 0;
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SPIFLASH.user.fwrite_dual = 0;
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SPIFLASH.user.fwrite_qio = 1;
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SPIFLASH.user.fwrite_quad = 0;
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SPIFLASH.ctrl.fcmd_dual = 0;
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SPIFLASH.ctrl.fcmd_quad = 0;
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SPIFLASH.user.usr_dummy = 0;
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SPIFLASH.user.usr_addr = 1;
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SPIFLASH.user.usr_command = 1;
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SPIFLASH.user2.usr_command_bitlen = 7;
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SPIFLASH.user2.usr_command_value = FLASH_WRAP_CMD;
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SPIFLASH.user1.usr_addr_bitlen = 23;
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SPIFLASH.addr = 0;
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SPIFLASH.user.usr_miso = 0;
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SPIFLASH.user.usr_mosi = 1;
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SPIFLASH.mosi_dlen.usr_mosi_bit_len = 7;
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SPIFLASH.data_buf[0] = (uint32_t) mode << 4;;
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SPIFLASH.cmd.usr = 1;
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while (SPIFLASH.cmd.usr != 0)
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{ }
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SPIFLASH.ctrl.val = reg_bkp_ctrl;
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SPIFLASH.user.val = reg_bkp_usr;
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return ESP_OK;
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}
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esp_err_t spi_flash_enable_wrap(uint32_t wrap_size)
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{
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switch (wrap_size) {
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case 8:
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return spi_flash_wrap_set(FLASH_WRAP_MODE_8B);
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case 16:
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return spi_flash_wrap_set(FLASH_WRAP_MODE_16B);
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case 32:
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return spi_flash_wrap_set(FLASH_WRAP_MODE_32B);
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case 64:
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return spi_flash_wrap_set(FLASH_WRAP_MODE_64B);
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default:
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return ESP_FAIL;
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}
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}
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void spi_flash_disable_wrap(void)
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{
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spi_flash_wrap_set(FLASH_WRAP_MODE_DISABLE);
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}
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bool spi_flash_support_wrap_size(uint32_t wrap_size)
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{
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if (!REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FREAD_QIO) || !REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FASTRD_MODE)) {
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return ESP_FAIL;
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}
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switch (wrap_size) {
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case 0:
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case 8:
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case 16:
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case 32:
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case 64:
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return true;
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default:
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return false;
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}
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}
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