kopia lustrzana https://github.com/espressif/esp-idf
176 wiersze
5.8 KiB
C
176 wiersze
5.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* This file is specified for I2S standard communication mode
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* Features:
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* - Philip/MSB/PCM are supported in standard mode
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* - Fixed to 2 slots
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*/
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#pragma once
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#include "hal/i2s_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_I2S_HW_VERSION_1 // For esp32/esp32-s2
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/**
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* @brief Philip format in 2 slots
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* @param bits_per_sample i2s data bit width
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* @param mono_or_stereo I2S_SLOT_MODE_MONO or I2S_SLOT_MODE_STEREO
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*/
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#define I2S_STD_PHILIP_SLOT_DEFAULT_CONFIG(bits_per_sample, mono_or_stereo) { \
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.mode = I2S_COMM_MODE_STD, \
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.data_bit_width = bits_per_sample, \
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.slot_bit_width = I2S_SLOT_BIT_WIDTH_DEFAULT, \
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.slot_mode = mono_or_stereo, \
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.ws_width = bits_per_sample, \
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.ws_pol = false, \
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.bit_shift = true, \
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.msb_right = false, \
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}
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/**
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* @brief PCM(short) format in 2 slots
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* @note PCM(long) is sample as philip in 2 slots
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* @param bits_per_sample i2s data bit width
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* @param mono_or_stereo I2S_SLOT_MODE_MONO or I2S_SLOT_MODE_STEREO
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*/
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#define I2S_STD_PCM_SLOT_DEFAULT_CONFIG(bits_per_sample, mono_or_stereo) { \
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.mode = I2S_COMM_MODE_STD, \
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.data_bit_width = bits_per_sample, \
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.slot_bit_width = I2S_SLOT_BIT_WIDTH_DEFAULT, \
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.slot_mode = mono_or_stereo, \
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.ws_width = 1, \
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.ws_pol = true, \
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.bit_shift = true, \
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.msb_right = false, \
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}
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/**
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* @brief MSB format in 2 slots
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* @param bits_per_sample i2s data bit width
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* @param mono_or_stereo I2S_SLOT_MODE_MONO or I2S_SLOT_MODE_STEREO
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*/
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#define I2S_STD_MSB_SLOT_DEFAULT_CONFIG(bits_per_sample, mono_or_stereo) { \
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.mode = I2S_COMM_MODE_STD, \
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.data_bit_width = bits_per_sample, \
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.slot_bit_width = I2S_SLOT_BIT_WIDTH_DEFAULT, \
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.slot_mode = mono_or_stereo, \
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.ws_width = bits_per_sample, \
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.ws_pol = false, \
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.bit_shift = false, \
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.msb_right = false, \
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}
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#else
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/**
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* @brief Philip format in 2 slots
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* @param bits_per_sample i2s data bit width
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* @param mono_or_stereo I2S_SLOT_MODE_MONO or I2S_SLOT_MODE_STEREO
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*/
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#define I2S_STD_PHILIP_SLOT_DEFAULT_CONFIG(bits_per_sample, mono_or_stereo) { \
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.mode = I2S_COMM_MODE_STD, \
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.data_bit_width = bits_per_sample, \
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.slot_bit_width = I2S_SLOT_BIT_WIDTH_DEFAULT, \
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.slot_mode = mono_or_stereo, \
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.ws_width = bits_per_sample, \
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.ws_pol = false, \
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.bit_shift = true, \
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.left_align = false, \
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.big_endian = false, \
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.bit_order_lsb = false \
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}
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/**
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* @brief PCM(short) format in 2 slots
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* @note PCM(long) is sample as philip in 2 slots
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* @param bits_per_sample i2s data bit width
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* @param mono_or_stereo I2S_SLOT_MODE_MONO or I2S_SLOT_MODE_STEREO
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*/
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#define I2S_STD_PCM_SLOT_DEFAULT_CONFIG(bits_per_sample, mono_or_stereo) { \
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.mode = I2S_COMM_MODE_STD, \
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.data_bit_width = bits_per_sample, \
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.slot_bit_width = I2S_SLOT_BIT_WIDTH_DEFAULT, \
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.slot_mode = mono_or_stereo, \
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.ws_width = 1, \
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.ws_pol = true, \
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.bit_shift = true, \
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.left_align = false, \
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.big_endian = false, \
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.bit_order_lsb = false \
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}
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/**
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* @brief MSB format in 2 slots
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* @param bits_per_sample i2s data bit width
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* @param mono_or_stereo I2S_SLOT_MODE_MONO or I2S_SLOT_MODE_STEREO
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*/
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#define I2S_STD_MSB_SLOT_DEFAULT_CONFIG(bits_per_sample, mono_or_stereo) { \
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.mode = I2S_COMM_MODE_STD, \
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.data_bit_width = bits_per_sample, \
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.slot_bit_width = I2S_SLOT_BIT_WIDTH_DEFAULT, \
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.slot_mode = mono_or_stereo, \
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.ws_width = bits_per_sample, \
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.ws_pol = false, \
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.bit_shift = false, \
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.left_align = false, \
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.big_endian = false, \
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.bit_order_lsb = false \
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}
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#endif
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/**
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* @brief i2s default standard clock configuration
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* @note Please set the mclk_multiple to I2S_MCLK_MULTIPLE_384 while using 24 bits data width
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* Otherwise the sample rate might be imprecise since the bclk division is not a integer
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* @param rate sample rate
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*/
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#define I2S_STD_CLK_DEFAULT_CONFIG(rate) { \
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.sample_rate_hz = rate, \
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.clk_src = I2S_CLK_D2CLK, \
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.mclk_multiple = I2S_MCLK_MULTIPLE_256, \
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}
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/**
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* @breif I2S slot configuration for standard mode
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*/
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typedef struct {
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/* General fields */
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i2s_comm_mode_t mode; /*!< I2S communication mode, this field is for identification (MUST match the communication mode in 'i2s_chan_config_t') */
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i2s_data_bit_width_t data_bit_width; /*!< I2S sample data bit width (valid data bits per sample) */
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i2s_slot_bit_width_t slot_bit_width; /*!< I2S slot bit width (total bits per slot) */
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i2s_slot_mode_t slot_mode; /*!< Set mono or stereo mode with I2S_SLOT_MODE_MONO or I2S_SLOT_MODE_STEREO */
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/* Particular fields */
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uint32_t ws_width; /*!< WS signal width (i.e. the number of bclk ticks that ws signal is high) */
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bool ws_pol; /*!< WS signal polarity, set true to enable high lever first */
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bool bit_shift; /*!< Set to enbale bit shift in Philip mode */
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#if SOC_I2S_HW_VERSION_1 // For esp32/esp32-s2
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bool msb_right; /*!< Set to place right channel data at the MSB in the FIFO */
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#else
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bool left_align; /*!< Set to enable left alignment */
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bool big_endian; /*!< Set to enable big endian */
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bool bit_order_lsb; /*!< Set to enable lsb first */
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#endif
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} i2s_std_slot_config_t;
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/**
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* @breif I2S clock configuration for standard mode
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*/
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typedef struct {
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/* General fields */
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uint32_t sample_rate_hz; /*!< I2S sample rate */
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i2s_clock_src_t clk_src; /*!< Choose clock source */
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i2s_mclk_multiple_t mclk_multiple; /*!< The multiple of mclk to the sample rate */
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} i2s_std_clk_config_t;
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#ifdef __cplusplus
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}
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#endif
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