kopia lustrzana https://github.com/espressif/esp-idf
86 wiersze
2.6 KiB
C
86 wiersze
2.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Switch CPU clock source to XTAL, and let cpu frequency equal to main XTAL frequency.
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*
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* This function does not disable CPU's source PLL. If the PLL requires to be disabled to save power, please call
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* `rtc_clk_cpu_freq_set_xtal` instead. It does one extra check (if necessary) to see whether can disable the
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* corresponding PLL after switching the CPU clock source to XTAL.
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*
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* Currently, this function should only be called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU
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* clock source back to XTAL (by default) before reset.
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*/
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void rtc_clk_cpu_set_to_default_config(void);
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/**
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* @brief Notify that the BBPLL has a new in-use consumer
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*
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* Currently, this function is only used for tracking whether USB Serial/JTAG is using the 48MHz PHY clock
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*
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* Note: Calling this function only helps to not disable the BBPLL clock in `rtc_clk_cpu_freq_set_config`.
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* For light and deep sleep, whether to disable the BBPLL in the internal call to `rtc_clk_cpu_freq_set_xtal`
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* varies for targets.
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* On ESP32C3/S3, USB CDC device can not function properly during sleep due to the lack of APB clock. Therefore.
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* `rtc_clk_cpu_freq_set_xtal` will always disable BBPLL, no matter whether BBPLL has any consumer.
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* On ESP32C6/H2, USB CDC device can maintain the minimum connection with the host during sleep, so
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* `rtc_clk_cpu_freq_set_xtal` will check for BBPLL consumers, and keep BBPLL if USB Serial/JTAG is in use.
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*/
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void rtc_clk_bbpll_add_consumer(void);
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/**
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* @brief Notify that the BBPLL has lost a consumer
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*/
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void rtc_clk_bbpll_remove_consumer(void);
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#if SOC_CLK_MPLL_SUPPORTED
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//------------------------------------MPLL-------------------------------------//
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/**
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* @brief Enable MPLL
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*/
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void rtc_clk_mpll_enable(void);
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/**
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* @brief Disable MPLL
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*/
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void rtc_clk_mpll_disable(void);
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/**
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* @brief Configure MPLL
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*
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* @param[in] xtal_freq XTAL frequency
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* @param[in] mpll_freq MPLL frequency
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*/
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void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq);
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/**
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* Get the MPLL frequency
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* @return the value of MPLL frequency in MHz
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*/
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uint32_t rtc_clk_mpll_get_freq(void);
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#endif //#if SOC_CLK_MPLL_SUPPORTED
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/**
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* @brief Workaround for C2, S3, C6, H2. Trigger the calibration of PLL. Should be called when the bootloader doesn't provide a good enough PLL accuracy.
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*/
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void rtc_clk_recalib_bbpll(void);
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#ifdef __cplusplus
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}
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#endif
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