kopia lustrzana https://github.com/espressif/esp-idf
52 wiersze
2.9 KiB
C
52 wiersze
2.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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//+-----------------------------------------------Terminology---------------------------------------------+
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//| |
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//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
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//| |
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//| Core Reset: Reset the whole digital system except RTC sub-system |
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//| |
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//| System Reset: Reset the whole digital system, including RTC sub-system |
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//| |
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//| Chip Reset: Reset the whole chip, including the analog part |
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//| |
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//+-------------------------------------------------------------------------------------------------------+
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
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* @note refer to TRM: <Reset and Clock> chapter
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*/
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typedef enum {
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RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
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RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
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RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip
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RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
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RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
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RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
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RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
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RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
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RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
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RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
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RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
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RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
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RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
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RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
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RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
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RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
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RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
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} soc_reset_reason_t;
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#ifdef __cplusplus
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}
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#endif
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