kopia lustrzana https://github.com/espressif/esp-idf
301dacfb33
Configurable option to use IRAM as byte accessible memory (in single core mode) using load-store (non-word aligned and non-word size IRAM access specific) exception handlers. This allows to use IRAM for use-cases where certain performance penalty (upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration option has been provided to redirect mbedTLS specific in-out content length buffers to IRAM (in single core mode), allows to save 20KB per TLS connection. |
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| .. | ||
| include/freertos | ||
| port.c | ||
| portasm.S | ||
| portmacro_priv.h | ||
| readme_xtensa.txt | ||
| xt_asm_utils.h | ||
| xtensa_context.S | ||
| xtensa_init.c | ||
| xtensa_intr.c | ||
| xtensa_intr_asm.S | ||
| xtensa_loadstore_handler.S | ||
| xtensa_overlay_os_hook.c | ||
| xtensa_vector_defaults.S | ||
| xtensa_vectors.S | ||