kopia lustrzana https://github.com/espressif/esp-idf
132 wiersze
5.4 KiB
C
132 wiersze
5.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief The contents defined in this file are common for both AXI-DMA and AHB-DMA
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/hp_sys_clkrst_struct.h"
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#include "soc/soc_etm_source.h"
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#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
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#define GDMA_LL_RX_EVENT_MASK (0x1F)
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#define GDMA_LL_TX_EVENT_MASK (0x0F)
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#define GDMA_LL_INVALID_PERIPH_ID (0x3F)
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#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3)
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#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2)
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#define GDMA_LL_EVENT_TX_EOF (1<<1)
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#define GDMA_LL_EVENT_TX_DONE (1<<0)
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#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4)
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#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3)
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#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2)
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#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1)
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#define GDMA_LL_EVENT_RX_DONE (1<<0)
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#define GDMA_LL_AHB_GROUP_START_ID 0 // AHB GDMA group ID starts from 0
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#define GDMA_LL_AHB_NUM_GROUPS 1 // Number of AHB GDMA groups
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#define GDMA_LL_AHB_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AHB group
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#define GDMA_LL_AXI_GROUP_START_ID 1 // AXI GDMA group ID starts from 1
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#define GDMA_LL_AXI_NUM_GROUPS 1 // Number of AXI GDMA groups
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#define GDMA_LL_AXI_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AXI group
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#define GDMA_LL_PARALLEL_CRC_DATA_WIDTH 8 // Parallel CRC data width is fixed to 8bits
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#define GDMA_LL_AHB_MAX_CRC_BIT_WIDTH 32 // Max CRC bit width supported by AHB GDMA
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#define GDMA_LL_AXI_MAX_CRC_BIT_WIDTH 16 // Max CRC bit width supported by AXI GDMA
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#define GDMA_LL_AHB_DESC_ALIGNMENT 4
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#define GDMA_LL_AXI_DESC_ALIGNMENT 8
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#define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \
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(uint32_t[2][GDMA_ETM_EVENT_MAX]){ \
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{ \
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[GDMA_ETM_EVENT_EOF] = PDMA_AHB_EVT_OUT_EOF_CH0 + (chan), \
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}, \
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{ \
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[GDMA_ETM_EVENT_EOF] = PDMA_AXI_EVT_OUT_EOF_CH0 + (chan), \
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}, \
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}[group][event]
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#define GDMA_LL_RX_ETM_EVENT_TABLE(group, chan, event) \
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(uint32_t[2][GDMA_ETM_EVENT_MAX]){ \
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{ \
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[GDMA_ETM_EVENT_EOF] = PDMA_AHB_EVT_IN_SUC_EOF_CH0 + (chan), \
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}, \
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{ \
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[GDMA_ETM_EVENT_EOF] = PDMA_AXI_EVT_IN_SUC_EOF_CH0 + (chan), \
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}, \
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}[group][event]
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#define GDMA_LL_TX_ETM_TASK_TABLE(group, chan, task) \
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(uint32_t[2][GDMA_ETM_TASK_MAX]){ \
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{ \
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[GDMA_ETM_TASK_START] = PDMA_AHB_TASK_OUT_START_CH0 + (chan), \
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}, \
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{ \
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[GDMA_ETM_TASK_START] = PDMA_AXI_TASK_OUT_START_CH0 + (chan), \
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}, \
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}[group][task]
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#define GDMA_LL_RX_ETM_TASK_TABLE(group, chan, task) \
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(uint32_t[2][GDMA_ETM_TASK_MAX]){ \
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{ \
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[GDMA_ETM_TASK_START] = PDMA_AHB_TASK_IN_START_CH0 + (chan), \
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}, \
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{ \
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[GDMA_ETM_TASK_START] = PDMA_AXI_TASK_IN_START_CH0 + (chan), \
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}, \
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}[group][task]
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Enable the bus clock for the DMA module
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*/
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static inline void gdma_ll_enable_bus_clock(int group_id, bool enable)
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{
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if (group_id == 0) {
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HP_SYS_CLKRST.soc_clk_ctrl1.reg_ahb_pdma_sys_clk_en = enable;
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} else {
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HP_SYS_CLKRST.soc_clk_ctrl1.reg_axi_pdma_sys_clk_en = enable;
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}
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define gdma_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; gdma_ll_enable_bus_clock(__VA_ARGS__)
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/**
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* @brief Reset the DMA module
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*/
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static inline void gdma_ll_reset_register(int group_id)
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{
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if (group_id == 0) {
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HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_ahb_pdma = 1;
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HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_ahb_pdma = 0;
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} else {
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HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_axi_pdma = 1;
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HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_axi_pdma = 0;
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}
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define gdma_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; gdma_ll_reset_register(__VA_ARGS__)
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#ifdef __cplusplus
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}
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#endif
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