kopia lustrzana https://github.com/espressif/esp-idf
96 wiersze
3.0 KiB
C
96 wiersze
3.0 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "freertos/FreeRTOS.h"
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#include "soc/periph_defs.h"
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#include "soc/soc_memory_layout.h"
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#include "hal/cp_dma_hal.h"
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#include "hal/cp_dma_ll.h"
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#include "esp_log.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_async_memcpy_impl.h"
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IRAM_ATTR static void async_memcpy_impl_default_isr_handler(void *args)
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{
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async_memcpy_impl_t *mcp_impl = (async_memcpy_impl_t *)args;
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portENTER_CRITICAL_ISR(&mcp_impl->hal_lock);
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uint32_t status = cp_dma_hal_get_intr_status(&mcp_impl->hal);
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cp_dma_hal_clear_intr_status(&mcp_impl->hal, status);
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portEXIT_CRITICAL_ISR(&mcp_impl->hal_lock);
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// End-Of-Frame on RX side
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if (status & CP_DMA_LL_EVENT_RX_EOF) {
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async_memcpy_isr_on_rx_done_event(mcp_impl);
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}
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if (mcp_impl->isr_need_yield) {
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mcp_impl->isr_need_yield = false;
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portYIELD_FROM_ISR();
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}
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}
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esp_err_t async_memcpy_impl_allocate_intr(async_memcpy_impl_t *impl, int int_flags, intr_handle_t *intr)
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{
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return esp_intr_alloc(ETS_DMA_COPY_INTR_SOURCE, int_flags, async_memcpy_impl_default_isr_handler, impl, intr);
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}
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esp_err_t async_memcpy_impl_init(async_memcpy_impl_t *impl, dma_descriptor_t *outlink_base, dma_descriptor_t *inlink_base)
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{
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impl->hal_lock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
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cp_dma_hal_config_t config = {
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.inlink_base = inlink_base,
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.outlink_base = outlink_base
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};
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cp_dma_hal_init(&impl->hal, &config);
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return ESP_OK;
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}
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esp_err_t async_memcpy_impl_deinit(async_memcpy_impl_t *impl)
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{
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cp_dma_hal_deinit(&impl->hal);
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return ESP_OK;
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}
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esp_err_t async_memcpy_impl_start(async_memcpy_impl_t *impl)
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{
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cp_dma_hal_start(&impl->hal); // enable DMA and interrupt
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return ESP_OK;
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}
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esp_err_t async_memcpy_impl_stop(async_memcpy_impl_t *impl)
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{
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cp_dma_hal_stop(&impl->hal); // disable DMA and interrupt
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return ESP_OK;
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}
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esp_err_t async_memcpy_impl_restart(async_memcpy_impl_t *impl)
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{
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cp_dma_hal_restart_rx(&impl->hal);
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cp_dma_hal_restart_tx(&impl->hal);
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return ESP_OK;
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}
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bool async_memcpy_impl_is_buffer_address_valid(async_memcpy_impl_t *impl, void *src, void *dst)
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{
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// CP_DMA can only access SRAM
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return esp_ptr_internal(src) && esp_ptr_internal(dst);
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}
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dma_descriptor_t *async_memcpy_impl_get_rx_suc_eof_descriptor(async_memcpy_impl_t *impl)
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{
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return (dma_descriptor_t *)cp_dma_ll_get_rx_eof_descriptor_address(impl->hal.dev);
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}
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