kopia lustrzana https://github.com/espressif/esp-idf
149 wiersze
5.3 KiB
C
149 wiersze
5.3 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// The HAL layer for ADC (ESP32-S2 specific part)
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#include "sdkconfig.h"
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#include "hal/adc_hal.h"
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#include "hal/adc_types.h"
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#include "hal/adc_hal_conf.h"
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#include "esp_log.h"
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/*---------------------------------------------------------------
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Digital controller setting
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---------------------------------------------------------------*/
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void adc_hal_digi_deinit(void)
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{
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adc_ll_digi_trigger_disable(); // boss
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adc_ll_digi_dma_disable();
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adc_ll_digi_clear_pattern_table(ADC_NUM_1);
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adc_ll_digi_clear_pattern_table(ADC_NUM_2);
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adc_ll_digi_filter_reset(ADC_NUM_1);
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adc_ll_digi_filter_reset(ADC_NUM_2);
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adc_ll_digi_reset();
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adc_ll_digi_controller_clk_disable();
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adc_hal_deinit();
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}
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void adc_hal_digi_controller_config(const adc_digi_config_t *cfg)
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{
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/* If enable digtal controller, adc xpd should always on. */
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adc_ll_set_power_manage(ADC_POWER_SW_ON);
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/* Single channel mode or multi channel mode. */
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adc_ll_digi_set_convert_mode(cfg->conv_mode);
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if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) {
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if (cfg->adc1_pattern_len) {
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adc_ll_digi_clear_pattern_table(ADC_NUM_1);
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adc_ll_digi_set_pattern_table_len(ADC_NUM_1, cfg->adc1_pattern_len);
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for (uint32_t i = 0; i < cfg->adc1_pattern_len; i++) {
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adc_ll_digi_set_pattern_table(ADC_NUM_1, i, cfg->adc1_pattern[i]);
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}
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}
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}
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if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_2) {
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if (cfg->adc2_pattern_len) {
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adc_ll_digi_clear_pattern_table(ADC_NUM_2);
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adc_ll_digi_set_pattern_table_len(ADC_NUM_2, cfg->adc2_pattern_len);
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for (uint32_t i = 0; i < cfg->adc2_pattern_len; i++) {
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adc_ll_digi_set_pattern_table(ADC_NUM_2, i, cfg->adc2_pattern[i]);
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}
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}
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}
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if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) {
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adc_ll_set_controller(ADC_NUM_1, ADC_CTRL_DIG);
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}
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if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_2) {
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adc_ll_set_controller(ADC_NUM_2, ADC_CTRL_DIG);
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}
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adc_ll_digi_set_output_format(cfg->format);
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if (cfg->conv_limit_en) {
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adc_ll_digi_set_convert_limit_num(cfg->conv_limit_num);
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adc_ll_digi_convert_limit_enable();
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} else {
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adc_ll_digi_convert_limit_disable();
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}
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adc_ll_digi_set_trigger_interval(cfg->interval);
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adc_hal_digi_clk_config(&cfg->dig_clk);
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adc_ll_digi_dma_set_eof_num(cfg->dma_eof_num);
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}
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/**
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* Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock.
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* Enable clock and select clock source for ADC digital controller.
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* Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
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*
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* @note ADC and DAC digital controller share the same frequency divider.
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* Please set a reasonable frequency division factor to meet the sampling frequency of the ADC and the output frequency of the DAC.
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*
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* @param clk Refer to ``adc_digi_clk_t``.
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*/
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void adc_hal_digi_clk_config(const adc_digi_clk_t *clk)
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{
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adc_ll_digi_controller_clk_div(clk->div_num, clk->div_b, clk->div_a);
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adc_ll_digi_controller_clk_enable(clk->use_apll);
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}
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/**
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* Enable digital controller to trigger the measurement.
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*/
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void adc_hal_digi_enable(void)
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{
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adc_ll_digi_dma_enable();
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adc_ll_digi_trigger_enable();
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}
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/**
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* Disable digital controller to trigger the measurement.
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*/
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void adc_hal_digi_disable(void)
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{
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adc_ll_digi_trigger_disable();
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adc_ll_digi_dma_disable();
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}
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/**
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* Config monitor of adc digital controller.
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*
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* @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
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* @param adc_n ADC unit.
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* @param config Refer to ``adc_digi_monitor_t``.
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*/
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void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config)
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{
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adc_ll_digi_monitor_set_mode(adc_n, config->mode);
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adc_ll_digi_monitor_set_thres(adc_n, config->threshold);
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}
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/*---------------------------------------------------------------
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Common setting
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---------------------------------------------------------------*/
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/**
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* Config ADC2 module arbiter.
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* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
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* the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
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*
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* @note Only ADC2 support arbiter.
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* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
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* @note Default priority: Wi-Fi > RTC > Digital;
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*
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* @param config Refer to ``adc_arbiter_t``.
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*/
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void adc_hal_arbiter_config(adc_arbiter_t *config)
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{
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adc_ll_set_arbiter_work_mode(config->mode);
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adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri);
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}
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