kopia lustrzana https://github.com/espressif/esp-idf
220 wiersze
8.0 KiB
C
220 wiersze
8.0 KiB
C
/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** TRACE_MEM_START_ADDR_REG register
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* mem start addr
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*/
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#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
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/** TRACE_MEM_STAET_ADDR : R/W; bitpos: [31:0]; default: 0;
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* The start address of trace memory
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*/
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#define TRACE_MEM_STAET_ADDR 0xFFFFFFFFU
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#define TRACE_MEM_STAET_ADDR_M (TRACE_MEM_STAET_ADDR_V << TRACE_MEM_STAET_ADDR_S)
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#define TRACE_MEM_STAET_ADDR_V 0xFFFFFFFFU
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#define TRACE_MEM_STAET_ADDR_S 0
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/** TRACE_MEM_END_ADDR_REG register
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* mem end addr
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*/
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#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4)
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/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
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* The end address of trace memory
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*/
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#define TRACE_MEM_END_ADDR 0xFFFFFFFFU
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#define TRACE_MEM_END_ADDR_M (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
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#define TRACE_MEM_END_ADDR_V 0xFFFFFFFFU
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#define TRACE_MEM_END_ADDR_S 0
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/** TRACE_MEM_CURRENT_ADDR_REG register
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* mem current addr
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*/
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#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8)
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/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
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* current_mem_addr,indicate that next writing addr
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*/
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#define TRACE_MEM_CURRENT_ADDR 0xFFFFFFFFU
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#define TRACE_MEM_CURRENT_ADDR_M (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
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#define TRACE_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
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#define TRACE_MEM_CURRENT_ADDR_S 0
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/** TRACE_MEM_ADDR_UPDATE_REG register
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* mem addr update
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*/
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#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc)
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/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
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* when set this reg, the current_mem_addr will update to start_addr
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*/
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#define TRACE_MEM_CURRENT_ADDR_UPDATE (BIT(0))
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#define TRACE_MEM_CURRENT_ADDR_UPDATE_M (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
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#define TRACE_MEM_CURRENT_ADDR_UPDATE_V 0x00000001U
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#define TRACE_MEM_CURRENT_ADDR_UPDATE_S 0
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/** TRACE_FIFO_STATUS_REG register
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* fifo status register
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*/
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#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
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/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
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* 1 indicate that fifo is empty
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*/
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#define TRACE_FIFO_EMPTY (BIT(0))
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#define TRACE_FIFO_EMPTY_M (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
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#define TRACE_FIFO_EMPTY_V 0x00000001U
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#define TRACE_FIFO_EMPTY_S 0
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/** TRACE_WORK_STATUS : RO; bitpos: [1]; default: 0;
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* mem_full interrupt status
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*/
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#define TRACE_WORK_STATUS (BIT(1))
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#define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
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#define TRACE_WORK_STATUS_V 0x00000001U
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#define TRACE_WORK_STATUS_S 1
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/** TRACE_INTR_ENA_REG register
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* interrupt enable register
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*/
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#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14)
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/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
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* Set 1 enable fifo_overflow interrupt
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*/
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#define TRACE_FIFO_OVERFLOW_INTR_ENA (BIT(0))
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#define TRACE_FIFO_OVERFLOW_INTR_ENA_M (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
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#define TRACE_FIFO_OVERFLOW_INTR_ENA_V 0x00000001U
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#define TRACE_FIFO_OVERFLOW_INTR_ENA_S 0
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/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
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* Set 1 enable mem_full interrupt
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*/
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#define TRACE_MEM_FULL_INTR_ENA (BIT(1))
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#define TRACE_MEM_FULL_INTR_ENA_M (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
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#define TRACE_MEM_FULL_INTR_ENA_V 0x00000001U
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#define TRACE_MEM_FULL_INTR_ENA_S 1
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/** TRACE_INTR_RAW_REG register
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* interrupt status register
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*/
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#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18)
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/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
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* fifo_overflow interrupt status
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*/
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#define TRACE_FIFO_OVERFLOW_INTR_RAW (BIT(0))
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#define TRACE_FIFO_OVERFLOW_INTR_RAW_M (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
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#define TRACE_FIFO_OVERFLOW_INTR_RAW_V 0x00000001U
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#define TRACE_FIFO_OVERFLOW_INTR_RAW_S 0
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/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
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* mem_full interrupt status
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*/
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#define TRACE_MEM_FULL_INTR_RAW (BIT(1))
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#define TRACE_MEM_FULL_INTR_RAW_M (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
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#define TRACE_MEM_FULL_INTR_RAW_V 0x00000001U
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#define TRACE_MEM_FULL_INTR_RAW_S 1
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/** TRACE_INTR_CLR_REG register
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* interrupt clear register
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*/
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#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c)
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/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
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* Set 1 clr fifo overflow interrupt
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*/
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#define TRACE_FIFO_OVERFLOW_INTR_CLR (BIT(0))
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#define TRACE_FIFO_OVERFLOW_INTR_CLR_M (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
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#define TRACE_FIFO_OVERFLOW_INTR_CLR_V 0x00000001U
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#define TRACE_FIFO_OVERFLOW_INTR_CLR_S 0
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/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
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* Set 1 clr mem full interrupt
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*/
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#define TRACE_MEM_FULL_INTR_CLR (BIT(1))
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#define TRACE_MEM_FULL_INTR_CLR_M (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
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#define TRACE_MEM_FULL_INTR_CLR_V 0x00000001U
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#define TRACE_MEM_FULL_INTR_CLR_S 1
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/** TRACE_TRIGGER_REG register
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* trigger register
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*/
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#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
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/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
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* [0] set 1 start trace.
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*/
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#define TRACE_TRIGGER_ON (BIT(0))
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#define TRACE_TRIGGER_ON_M (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
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#define TRACE_TRIGGER_ON_V 0x00000001U
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#define TRACE_TRIGGER_ON_S 0
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/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
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* set 1 stop trace.
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*/
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#define TRACE_TRIGGER_OFF (BIT(1))
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#define TRACE_TRIGGER_OFF_M (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
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#define TRACE_TRIGGER_OFF_V 0x00000001U
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#define TRACE_TRIGGER_OFF_S 1
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/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
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* if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr
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* at mem_end_addr, it will stop at the mem_end_addr
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*/
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#define TRACE_MEM_LOOP (BIT(2))
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#define TRACE_MEM_LOOP_M (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
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#define TRACE_MEM_LOOP_V 0x00000001U
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#define TRACE_MEM_LOOP_S 2
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/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
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* enable encoder auto-restart, when lost package, the encoder will end, if enable
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* auto-restart, when fifo empty, encoder will restart and send a sync package.
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*/
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#define TRACE_RESTART_ENA (BIT(3))
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#define TRACE_RESTART_ENA_M (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
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#define TRACE_RESTART_ENA_V 0x00000001U
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#define TRACE_RESTART_ENA_S 3
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/** TRACE_RESYNC_PROLONGED_REG register
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* resync configuration register
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*/
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#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x24)
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/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
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* count number, when count to this value, send a sync package
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*/
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#define TRACE_RESYNC_PROLONGED 0x00FFFFFFU
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#define TRACE_RESYNC_PROLONGED_M (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
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#define TRACE_RESYNC_PROLONGED_V 0x00FFFFFFU
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#define TRACE_RESYNC_PROLONGED_S 0
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/** TRACE_RESYNC_MODE : R/W; bitpos: [24]; default: 0;
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* resyc mode sel: 0: default, cycle count 1: package num count
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*/
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#define TRACE_RESYNC_MODE (BIT(24))
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#define TRACE_RESYNC_MODE_M (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
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#define TRACE_RESYNC_MODE_V 0x00000001U
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#define TRACE_RESYNC_MODE_S 24
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/** TRACE_CLOCK_GATE_REG register
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* Clock gate control register
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*/
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#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x28)
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/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
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* The bit is used to enable clock gate when access all registers in this module.
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*/
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#define TRACE_CLK_EN (BIT(0))
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#define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
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#define TRACE_CLK_EN_V 0x00000001U
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#define TRACE_CLK_EN_S 0
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/** TRACE_DATE_REG register
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* Version control register
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*/
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#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc)
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/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35663920;
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* version control register. Note that this default value stored is the latest date
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* when the hardware logic was updated.
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*/
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#define TRACE_DATE 0x0FFFFFFFU
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#define TRACE_DATE_M (TRACE_DATE_V << TRACE_DATE_S)
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#define TRACE_DATE_V 0x0FFFFFFFU
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#define TRACE_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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