kopia lustrzana https://github.com/espressif/esp-idf
411 wiersze
14 KiB
C
411 wiersze
14 KiB
C
/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include "unity.h"
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#include "esp_attr.h"
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#include "soc/soc_caps.h"
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#include "soc/rtc.h"
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#include "soc/rtc_periph.h"
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#if SOC_ADC_RTC_CTRL_SUPPORTED
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#include "soc/sens_periph.h"
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#endif
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#include "soc/gpio_periph.h"
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#include "hal/gpio_ll.h"
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#include "driver/rtc_io.h"
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#include "test_utils.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_sys.h"
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#include "esp_rom_uart.h"
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#include "esp_sleep.h"
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#include "esp_system.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rtc.h"
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#include "esp32/clk.h"
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#include "esp32/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rtc.h"
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#include "esp32s2/clk.h"
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#include "esp32s2/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rtc.h"
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#include "esp32s3/clk.h"
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#include "esp32s3/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rtc.h"
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#include "esp32c3/clk.h"
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#include "esp32c3/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32H2
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#include "esp32h2/rtc.h"
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#include "esp32h2/clk.h"
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#include "esp32h2/rom/rtc.h"
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#endif
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extern void rtc_clk_select_rtc_slow_clk(void);
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
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#define CALIBRATE_ONE(cali_clk) calibrate_one(cali_clk, #cali_clk)
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static uint32_t calibrate_one(rtc_cal_sel_t cal_clk, const char* name)
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{
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const uint32_t cal_count = 1000;
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const float factor = (1 << 19) * 1000.0f;
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uint32_t cali_val;
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printf("%s:\n", name);
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for (int i = 0; i < 5; ++i) {
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printf("calibrate (%d): ", i);
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cali_val = rtc_clk_cal(cal_clk, cal_count);
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printf("%.3f kHz\n", factor / (float) cali_val);
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}
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return cali_val;
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}
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TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]")
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{
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rtc_clk_32k_enable(true);
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rtc_clk_8m_enable(true, true);
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CALIBRATE_ONE(RTC_CAL_RTC_MUX);
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CALIBRATE_ONE(RTC_CAL_8MD256);
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uint32_t cal_32k = CALIBRATE_ONE(RTC_CAL_32K_XTAL);
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if (cal_32k == 0) {
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printf("32K XTAL OSC has not started up");
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} else {
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printf("switching to RTC_SLOW_FREQ_32K_XTAL: ");
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rtc_clk_slow_freq_set(RTC_SLOW_FREQ_32K_XTAL);
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printf("done\n");
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CALIBRATE_ONE(RTC_CAL_RTC_MUX);
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CALIBRATE_ONE(RTC_CAL_8MD256);
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CALIBRATE_ONE(RTC_CAL_32K_XTAL);
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}
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printf("switching to RTC_SLOW_FREQ_8MD256: ");
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rtc_clk_slow_freq_set(RTC_SLOW_FREQ_8MD256);
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printf("done\n");
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CALIBRATE_ONE(RTC_CAL_RTC_MUX);
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CALIBRATE_ONE(RTC_CAL_8MD256);
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CALIBRATE_ONE(RTC_CAL_32K_XTAL);
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}
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/* The following two are not unit tests, but are added here to make it easy to
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* check the frequency of 150k/32k oscillators. The following two "tests" will
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* output either 32k or 150k clock to GPIO25.
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*/
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static void pull_out_clk(int sel)
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{
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REG_SET_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M);
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REG_CLR_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_RDE_M | RTC_IO_PDAC1_RUE_M);
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REG_SET_FIELD(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_FUN_SEL, 1);
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REG_SET_FIELD(SENS_SAR_DAC_CTRL1_REG, SENS_DEBUG_BIT_SEL, 0);
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REG_SET_FIELD(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_SEL0, sel);
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}
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TEST_CASE("Output 150k clock to GPIO25", "[rtc_clk][ignore]")
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{
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pull_out_clk(RTC_IO_DEBUG_SEL0_150K_OSC);
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}
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TEST_CASE("Output 32k XTAL clock to GPIO25", "[rtc_clk][ignore]")
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{
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rtc_clk_32k_enable(true);
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pull_out_clk(RTC_IO_DEBUG_SEL0_32K_XTAL);
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}
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TEST_CASE("Output 8M XTAL clock to GPIO25", "[rtc_clk][ignore]")
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{
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rtc_clk_8m_enable(true, true);
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SET_PERI_REG_MASK(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_12M_NO_GATING);
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pull_out_clk(RTC_IO_DEBUG_SEL0_8M);
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}
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static void test_clock_switching(void (*switch_func)(const rtc_cpu_freq_config_t* config))
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{
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esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
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const int test_duration_sec = 10;
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ref_clock_init();
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uint64_t t_start = ref_clock_get();
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rtc_cpu_freq_config_t cur_config;
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rtc_clk_cpu_freq_get_config(&cur_config);
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rtc_cpu_freq_config_t xtal_config;
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rtc_clk_cpu_freq_mhz_to_config((uint32_t) rtc_clk_xtal_freq_get(), &xtal_config);
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int count = 0;
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while (ref_clock_get() - t_start < test_duration_sec * 1000000) {
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switch_func(&xtal_config);
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switch_func(&cur_config);
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++count;
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}
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uint64_t t_end = ref_clock_get();
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printf("Switch count: %d. Average time to switch PLL -> XTAL -> PLL: %d us\n", count, (int) ((t_end - t_start) / count));
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ref_clock_deinit();
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}
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TEST_CASE("Calculate 8M clock frequency", "[rtc_clk]")
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{
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// calibrate 8M/256 clock against XTAL, get 8M/256 clock period
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uint32_t rtc_8md256_period = rtc_clk_cal(RTC_CAL_8MD256, 100);
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uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period;
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printf("RTC_FAST_CLK=%d Hz\n", rtc_fast_freq_hz);
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TEST_ASSERT_INT32_WITHIN(650000, RTC_FAST_CLK_FREQ_APPROX, rtc_fast_freq_hz);
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}
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TEST_CASE("Test switching between PLL and XTAL", "[rtc_clk]")
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{
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test_clock_switching(rtc_clk_cpu_freq_set_config);
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}
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TEST_CASE("Test fast switching between PLL and XTAL", "[rtc_clk]")
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{
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test_clock_switching(rtc_clk_cpu_freq_set_config_fast);
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}
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/* In CI environments, the 32kXTAL runners don't have 8MB psram for bank switching.
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So can only test one config or the other. */
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#if !IDF_CI_BUILD || !CONFIG_SPIRAM_BANKSWITCH_ENABLE
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#define COUNT_TEST 3
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#define TIMEOUT_TEST_MS (5 + CONFIG_ESP32_RTC_CLK_CAL_CYCLES / 16)
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void stop_rtc_external_quartz(void){
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const uint8_t pin_32 = 32;
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const uint8_t pin_33 = 33;
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rtc_clk_32k_enable(false);
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esp_rom_gpio_pad_select_gpio(pin_32);
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esp_rom_gpio_pad_select_gpio(pin_33);
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gpio_ll_output_enable(&GPIO, pin_32);
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gpio_ll_output_enable(&GPIO, pin_33);
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gpio_ll_set_level(&GPIO, pin_32, 0);
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gpio_ll_set_level(&GPIO, pin_33, 0);
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esp_rom_delay_us(500000);
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gpio_ll_output_disable(&GPIO, pin_32);
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gpio_ll_output_disable(&GPIO, pin_33);
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}
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static void start_freq(rtc_slow_freq_t required_src_freq, uint32_t start_delay_ms)
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{
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int i = 0, fail = 0;
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uint32_t start_time;
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uint32_t end_time;
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rtc_slow_freq_t selected_src_freq;
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stop_rtc_external_quartz();
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#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
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uint32_t bootstrap_cycles = CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES;
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printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
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bootstrap_cycles,
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CONFIG_ESP32_RTC_CLK_CAL_CYCLES);
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#else
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uint32_t bootstrap_cycles = 5;
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printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
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bootstrap_cycles,
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CONFIG_ESP32_RTC_CLK_CAL_CYCLES);
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#endif // CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
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if (start_delay_ms == 0 && CONFIG_ESP32_RTC_CLK_CAL_CYCLES < 1500){
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start_delay_ms = 50;
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printf("Recommended increase Number of cycles for RTC_SLOW_CLK calibration to 3000!\n");
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}
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while(i < COUNT_TEST){
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start_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
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i++;
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printf("attempt #%d/%d...", i, COUNT_TEST);
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rtc_clk_32k_bootstrap(bootstrap_cycles);
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esp_rom_delay_us(start_delay_ms * 1000);
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rtc_clk_select_rtc_slow_clk();
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selected_src_freq = rtc_clk_slow_freq_get();
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end_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
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printf(" [time=%d] ", (end_time - start_time) - start_delay_ms);
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if(selected_src_freq != required_src_freq){
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printf("FAIL. Time measurement...");
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fail = 1;
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} else {
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printf("PASS. Time measurement...");
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}
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uint64_t clk_rtc_time;
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uint32_t fail_measure = 0;
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for (int j = 0; j < 3; ++j) {
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clk_rtc_time = esp_clk_rtc_time();
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esp_rom_delay_us(1000000);
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uint64_t delta = esp_clk_rtc_time() - clk_rtc_time;
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if (delta < 900000LL || delta > 1100000){
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printf("FAIL");
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fail = 1;
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fail_measure = 1;
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break;
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}
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}
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if(fail_measure == 0) {
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printf("PASS");
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}
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printf(" [calibration val = %d] \n", esp_clk_slowclk_cal_get());
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stop_rtc_external_quartz();
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esp_rom_delay_us(500000);
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}
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TEST_ASSERT_MESSAGE(fail == 0, "Test failed");
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printf("Test passed successfully\n");
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}
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TEST_CASE("Test starting external RTC quartz", "[rtc_clk][test_env=UT_T1_32kXTAL]")
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{
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int i = 0, fail = 0;
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uint32_t start_time;
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uint32_t end_time;
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stop_rtc_external_quartz();
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#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
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uint32_t bootstrap_cycles = CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES;
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printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
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bootstrap_cycles,
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CONFIG_ESP32_RTC_CLK_CAL_CYCLES);
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#else
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uint32_t bootstrap_cycles = 5;
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printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
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bootstrap_cycles,
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CONFIG_ESP32_RTC_CLK_CAL_CYCLES);
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#endif // CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
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if (CONFIG_ESP32_RTC_CLK_CAL_CYCLES < 1500){
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printf("Recommended increase Number of cycles for RTC_SLOW_CLK calibration to 3000!\n");
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}
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while(i < COUNT_TEST){
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start_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
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i++;
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printf("attempt #%d/%d...", i, COUNT_TEST);
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rtc_clk_32k_bootstrap(bootstrap_cycles);
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rtc_clk_select_rtc_slow_clk();
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end_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
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printf(" [time=%d] ", end_time - start_time);
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if((end_time - start_time) > TIMEOUT_TEST_MS){
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printf("FAIL\n");
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fail = 1;
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} else {
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printf("PASS\n");
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}
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stop_rtc_external_quartz();
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esp_rom_delay_us(100000);
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}
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TEST_ASSERT_MESSAGE(fail == 0, "Test failed");
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printf("Test passed successfully\n");
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}
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TEST_CASE("Test starting 'External 32kHz XTAL' on the board with it.", "[rtc_clk][test_env=UT_T1_32kXTAL]")
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{
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start_freq(RTC_SLOW_FREQ_32K_XTAL, 200);
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start_freq(RTC_SLOW_FREQ_32K_XTAL, 0);
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}
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TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_clk][test_env=UT_T1_no32kXTAL]")
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{
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printf("Tries to start the 'External 32kHz XTAL' on the board without it. "
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"Clock switching to 'Internal 150 kHz RC oscillator'.\n");
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printf("This test will be successful for boards without an external crystal or non-working crystal. "
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"First, there will be an attempt to start from the external crystal after a failure "
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"will switch to the internal RC circuit. If the switch to the internal RC circuit "
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"was successful then the test succeeded.\n");
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start_freq(RTC_SLOW_FREQ_RTC, 200);
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start_freq(RTC_SLOW_FREQ_RTC, 0);
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}
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#endif // !IDF_CI_BUILD || !CONFIG_SPIRAM_BANKSWITCH_ENABLE
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#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
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TEST_CASE("Test rtc clk calibration compensation", "[rtc_clk]")
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{
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int64_t t1 = esp_rtc_get_time_us();
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// Modify calibration value
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esp_clk_slowclk_cal_set(esp_clk_slowclk_cal_get() / 2);
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// Delay for error accumulation.
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vTaskDelay(pdMS_TO_TICKS(1000));
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// Internally, the origin point of rtc clk has been adjusted
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// so that t2 > t1 remains true
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int64_t t2 = esp_rtc_get_time_us();
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TEST_ASSERT_GREATER_THAN(t1, t2);
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// Restore calibration value
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esp_clk_slowclk_cal_set(esp_clk_slowclk_cal_get() * 2);
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// Delay for error accumulation.
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vTaskDelay(pdMS_TO_TICKS(1000));
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t2 = esp_rtc_get_time_us();
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TEST_ASSERT_GREATER_THAN(t1, t2);
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}
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
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/* Disabled until deep sleep is brought up TODO ESP32-S3 IDF-2691 */
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static RTC_NOINIT_ATTR int64_t start = 0;
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static void trigger_deepsleep(void)
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{
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printf("Trigger deep sleep. Waiting for 10 sec ...\n");
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// Simulate the dispersion of the calibration coefficients at start-up.
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// Corrupt the calibration factor.
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esp_clk_slowclk_cal_set(esp_clk_slowclk_cal_get() / 2);
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// Delay for error accumulation.
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vTaskDelay(pdMS_TO_TICKS(1000));
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// Save start time. Deep sleep.
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start = esp_rtc_get_time_us();
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esp_sleep_enable_timer_wakeup(1000);
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// In function esp_deep_sleep_start() uses function esp_sync_counters_rtc_and_frc()
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// to prevent a negative time after wake up.
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esp_deep_sleep_start();
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}
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static void check_time_deepsleep_1(void)
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{
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soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
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TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
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int64_t end = esp_rtc_get_time_us();
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TEST_ASSERT_GREATER_THAN(start, end);
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esp_clk_slowclk_cal_set(esp_clk_slowclk_cal_get() * 2);
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// Delay for error accumulation.
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vTaskDelay(pdMS_TO_TICKS(1000));
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start = esp_rtc_get_time_us();
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esp_sleep_enable_timer_wakeup(1000);
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// In function esp_deep_sleep_start() uses function esp_sync_counters_rtc_and_frc()
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// to prevent a negative time after wake up.
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esp_deep_sleep_start();
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}
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static void check_time_deepsleep_2(void)
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{
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soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
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TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
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int64_t end = esp_rtc_get_time_us();
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TEST_ASSERT_GREATER_THAN(start, end);
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}
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TEST_CASE_MULTIPLE_STAGES("Test rtc clk calibration compensation across deep sleep", "[rtc_clk][reset=DEEPSLEEP_RESET, DEEPSLEEP_RESET]", trigger_deepsleep, check_time_deepsleep_1, check_time_deepsleep_2);
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#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
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