esp-idf/components/esp_hw_support/port/esp32s3
Armando c331c85318 mspi: make cpu clock source switch safe
For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required.
Certain delays will be added to the MSPI RX direction. When system clock switches down, the delays should be
cleared. When system clock switches up, the delays should be restored.
2021-10-19 21:47:27 +08:00
..
private_include
CMakeLists.txt
Kconfig.mac
chip_info.c
dport_access.c
esp_crypto_lock.c
esp_ds.c
esp_hmac.c
memprot.c
opiram_psram.c psram: put opiram_psram and spiram_psram in internal ram 2021-10-08 17:39:41 +08:00
regi2c_ctrl.h
rtc_clk.c
rtc_clk_common.h
rtc_clk_init.c
rtc_init.c mspi: make cpu clock source switch safe 2021-10-19 21:47:27 +08:00
rtc_pm.c
rtc_sleep.c Merge branch 'feature/ledc_use_rtc8m_or_xtal_lightsleep' into 'master' 2021-09-27 04:02:29 +00:00
rtc_time.c fix rtc_clk_cal: Wait for timeout in a loop instead of just judge once 2021-10-19 12:07:34 +08:00
rtc_wdt.c
spiram.c
spiram_psram.c psram: put opiram_psram and spiram_psram in internal ram 2021-10-08 17:39:41 +08:00
spiram_psram.h