kopia lustrzana https://github.com/espressif/esp-idf
844 wiersze
30 KiB
C
844 wiersze
30 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <string.h>
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#include <esp_types.h>
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#include <limits.h>
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#include <assert.h>
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp_intr_alloc.h"
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#include "esp_attr.h"
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#include "hal/cpu_hal.h"
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#include "esp_private/rtc_ctrl.h"
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#include "hal/interrupt_controller_hal.h"
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#if !CONFIG_FREERTOS_UNICORE
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#include "esp_ipc.h"
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#endif
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static const char* TAG = "intr_alloc";
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#define ETS_INTERNAL_TIMER0_INTR_NO 6
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#define ETS_INTERNAL_TIMER1_INTR_NO 15
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#define ETS_INTERNAL_TIMER2_INTR_NO 16
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#define ETS_INTERNAL_SW0_INTR_NO 7
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#define ETS_INTERNAL_SW1_INTR_NO 29
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#define ETS_INTERNAL_PROFILING_INTR_NO 11
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/*
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Define this to debug the choices made when allocating the interrupt. This leads to much debugging
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output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog
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being triggered, that is why it is separate from the normal LOG* scheme.
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*/
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// #define DEBUG_INT_ALLOC_DECISIONS
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#ifdef DEBUG_INT_ALLOC_DECISIONS
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# define ALCHLOG(...) ESP_EARLY_LOGD(TAG, __VA_ARGS__)
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#else
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# define ALCHLOG(...) do {} while (0)
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#endif
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typedef struct shared_vector_desc_t shared_vector_desc_t;
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typedef struct vector_desc_t vector_desc_t;
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struct shared_vector_desc_t {
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int disabled: 1;
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int source: 8;
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volatile uint32_t *statusreg;
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uint32_t statusmask;
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intr_handler_t isr;
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void *arg;
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shared_vector_desc_t *next;
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};
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#define VECDESC_FL_RESERVED (1<<0)
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#define VECDESC_FL_INIRAM (1<<1)
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#define VECDESC_FL_SHARED (1<<2)
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#define VECDESC_FL_NONSHARED (1<<3)
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//Pack using bitfields for better memory use
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struct vector_desc_t {
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int flags: 16; //OR of VECDESC_FL_* defines
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unsigned int cpu: 1;
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unsigned int intno: 5;
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int source: 8; //Interrupt mux flags, used when not shared
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shared_vector_desc_t *shared_vec_info; //used when VECDESC_FL_SHARED
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vector_desc_t *next;
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};
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struct intr_handle_data_t {
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vector_desc_t *vector_desc;
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shared_vector_desc_t *shared_vector_desc;
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};
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typedef struct non_shared_isr_arg_t non_shared_isr_arg_t;
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struct non_shared_isr_arg_t {
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intr_handler_t isr;
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void *isr_arg;
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int source;
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};
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//Linked list of vector descriptions, sorted by cpu.intno value
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static vector_desc_t *vector_desc_head = NULL;
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//This bitmask has an 1 if the int should be disabled when the flash is disabled.
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static uint32_t non_iram_int_mask[SOC_CPU_CORES_NUM];
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//This bitmask has 1 in it if the int was disabled using esp_intr_noniram_disable.
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static uint32_t non_iram_int_disabled[SOC_CPU_CORES_NUM];
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static bool non_iram_int_disabled_flag[SOC_CPU_CORES_NUM];
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static portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
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//Inserts an item into vector_desc list so that the list is sorted
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//with an incrementing cpu.intno value.
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static void insert_vector_desc(vector_desc_t *to_insert)
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{
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vector_desc_t *vd=vector_desc_head;
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vector_desc_t *prev=NULL;
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while(vd!=NULL) {
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if (vd->cpu > to_insert->cpu) break;
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if (vd->cpu == to_insert->cpu && vd->intno >= to_insert->intno) break;
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prev=vd;
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vd=vd->next;
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}
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if ((vector_desc_head==NULL) || (prev==NULL)) {
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//First item
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to_insert->next = vd;
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vector_desc_head=to_insert;
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} else {
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prev->next=to_insert;
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to_insert->next=vd;
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}
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}
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//Returns a vector_desc entry for an intno/cpu, or NULL if none exists.
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static vector_desc_t *find_desc_for_int(int intno, int cpu)
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{
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vector_desc_t *vd=vector_desc_head;
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while(vd!=NULL) {
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if (vd->cpu==cpu && vd->intno==intno) break;
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vd=vd->next;
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}
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return vd;
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}
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//Returns a vector_desc entry for an intno/cpu.
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//Either returns a preexisting one or allocates a new one and inserts
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//it into the list. Returns NULL on malloc fail.
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static vector_desc_t *get_desc_for_int(int intno, int cpu)
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{
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vector_desc_t *vd=find_desc_for_int(intno, cpu);
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if (vd==NULL) {
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vector_desc_t *newvd=heap_caps_malloc(sizeof(vector_desc_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
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if (newvd==NULL) return NULL;
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memset(newvd, 0, sizeof(vector_desc_t));
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newvd->intno=intno;
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newvd->cpu=cpu;
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insert_vector_desc(newvd);
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return newvd;
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} else {
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return vd;
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}
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}
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//Returns a vector_desc entry for an source, the cpu parameter is used to tell GPIO_INT and GPIO_NMI from different CPUs
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static vector_desc_t * find_desc_for_source(int source, int cpu)
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{
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vector_desc_t *vd=vector_desc_head;
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while(vd!=NULL) {
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if ( !(vd->flags & VECDESC_FL_SHARED) ) {
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if ( vd->source == source && cpu == vd->cpu ) break;
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} else if ( vd->cpu == cpu ) {
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// check only shared vds for the correct cpu, otherwise skip
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bool found = false;
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shared_vector_desc_t *svd = vd->shared_vec_info;
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assert(svd != NULL );
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while(svd) {
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if ( svd->source == source ) {
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found = true;
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break;
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}
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svd = svd->next;
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}
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if ( found ) break;
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}
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vd=vd->next;
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}
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return vd;
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}
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esp_err_t esp_intr_mark_shared(int intno, int cpu, bool is_int_ram)
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{
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if (intno>31) return ESP_ERR_INVALID_ARG;
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if (cpu>=SOC_CPU_CORES_NUM) return ESP_ERR_INVALID_ARG;
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portENTER_CRITICAL(&spinlock);
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vector_desc_t *vd=get_desc_for_int(intno, cpu);
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if (vd==NULL) {
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portEXIT_CRITICAL(&spinlock);
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return ESP_ERR_NO_MEM;
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}
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vd->flags=VECDESC_FL_SHARED;
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if (is_int_ram) vd->flags|=VECDESC_FL_INIRAM;
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portEXIT_CRITICAL(&spinlock);
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return ESP_OK;
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}
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esp_err_t esp_intr_reserve(int intno, int cpu)
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{
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if (intno>31) return ESP_ERR_INVALID_ARG;
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if (cpu>=SOC_CPU_CORES_NUM) return ESP_ERR_INVALID_ARG;
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portENTER_CRITICAL(&spinlock);
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vector_desc_t *vd=get_desc_for_int(intno, cpu);
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if (vd==NULL) {
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portEXIT_CRITICAL(&spinlock);
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return ESP_ERR_NO_MEM;
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}
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vd->flags=VECDESC_FL_RESERVED;
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portEXIT_CRITICAL(&spinlock);
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return ESP_OK;
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}
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static bool is_vect_desc_usable(vector_desc_t *vd, int flags, int cpu, int force)
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{
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//Check if interrupt is not reserved by design
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int x = vd->intno;
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if (interrupt_controller_hal_get_cpu_desc_flags(x, cpu)==INTDESC_RESVD) {
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ALCHLOG("....Unusable: reserved");
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return false;
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}
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if (interrupt_controller_hal_get_cpu_desc_flags(x, cpu)==INTDESC_SPECIAL && force==-1) {
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ALCHLOG("....Unusable: special-purpose int");
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return false;
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}
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#ifndef SOC_CPU_HAS_FLEXIBLE_INTC
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//Check if the interrupt level is acceptable
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if (!(flags&(1<<interrupt_controller_hal_get_level(x)))) {
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ALCHLOG("....Unusable: incompatible level");
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return false;
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}
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//check if edge/level type matches what we want
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if (((flags&ESP_INTR_FLAG_EDGE) && (interrupt_controller_hal_get_type(x)==INTTP_LEVEL)) ||
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(((!(flags&ESP_INTR_FLAG_EDGE)) && (interrupt_controller_hal_get_type(x)==INTTP_EDGE)))) {
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ALCHLOG("....Unusable: incompatible trigger type");
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return false;
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}
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#endif
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//check if interrupt is reserved at runtime
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if (vd->flags&VECDESC_FL_RESERVED) {
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ALCHLOG("....Unusable: reserved at runtime.");
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return false;
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}
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//Ints can't be both shared and non-shared.
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assert(!((vd->flags&VECDESC_FL_SHARED)&&(vd->flags&VECDESC_FL_NONSHARED)));
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//check if interrupt already is in use by a non-shared interrupt
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if (vd->flags&VECDESC_FL_NONSHARED) {
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ALCHLOG("....Unusable: already in (non-shared) use.");
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return false;
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}
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// check shared interrupt flags
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if (vd->flags&VECDESC_FL_SHARED ) {
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if (flags&ESP_INTR_FLAG_SHARED) {
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bool in_iram_flag=((flags&ESP_INTR_FLAG_IRAM)!=0);
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bool desc_in_iram_flag=((vd->flags&VECDESC_FL_INIRAM)!=0);
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//Bail out if int is shared, but iram property doesn't match what we want.
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if ((vd->flags&VECDESC_FL_SHARED) && (desc_in_iram_flag!=in_iram_flag)) {
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ALCHLOG("....Unusable: shared but iram prop doesn't match");
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return false;
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}
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} else {
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//We need an unshared IRQ; can't use shared ones; bail out if this is shared.
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ALCHLOG("...Unusable: int is shared, we need non-shared.");
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return false;
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}
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} else if (interrupt_controller_hal_has_handler(x, cpu)) {
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//Check if interrupt already is allocated by interrupt_controller_hal_set_int_handler
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ALCHLOG("....Unusable: already allocated");
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return false;
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}
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return true;
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}
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//Locate a free interrupt compatible with the flags given.
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//The 'force' argument can be -1, or 0-31 to force checking a certain interrupt.
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//When a CPU is forced, the INTDESC_SPECIAL marked interrupts are also accepted.
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static int get_available_int(int flags, int cpu, int force, int source)
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{
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int x;
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int best=-1;
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int bestLevel=9;
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int bestSharedCt=INT_MAX;
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//Default vector desc, for vectors not in the linked list
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vector_desc_t empty_vect_desc;
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memset(&empty_vect_desc, 0, sizeof(vector_desc_t));
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//Level defaults to any low/med interrupt
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if (!(flags&ESP_INTR_FLAG_LEVELMASK)) flags|=ESP_INTR_FLAG_LOWMED;
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ALCHLOG("get_available_int: try to find existing. Cpu: %d, Source: %d", cpu, source);
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vector_desc_t *vd = find_desc_for_source(source, cpu);
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if ( vd ) {
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// if existing vd found, don't need to search any more.
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ALCHLOG("get_avalible_int: existing vd found. intno: %d", vd->intno);
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if ( force != -1 && force != vd->intno ) {
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ALCHLOG("get_avalible_int: intr forced but not matach existing. existing intno: %d, force: %d", vd->intno, force);
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} else if ( !is_vect_desc_usable(vd, flags, cpu, force) ) {
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ALCHLOG("get_avalible_int: existing vd invalid.");
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} else {
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best = vd->intno;
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}
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return best;
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}
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if (force!=-1) {
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ALCHLOG("get_available_int: try to find force. Cpu: %d, Source: %d, Force: %d", cpu, source, force);
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//if force assigned, don't need to search any more.
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vd = find_desc_for_int(force, cpu);
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if (vd == NULL ) {
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//if existing vd not found, just check the default state for the intr.
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empty_vect_desc.intno = force;
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vd = &empty_vect_desc;
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}
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if ( is_vect_desc_usable(vd, flags, cpu, force) ) {
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best = vd->intno;
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} else {
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ALCHLOG("get_avalible_int: forced vd invalid.");
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}
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return best;
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}
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ALCHLOG("get_free_int: start looking. Current cpu: %d", cpu);
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//No allocated handlers as well as forced intr, iterate over the 32 possible interrupts
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for (x=0; x<32; x++) {
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//Grab the vector_desc for this vector.
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vd=find_desc_for_int(x, cpu);
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if (vd==NULL) {
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empty_vect_desc.intno = x;
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vd=&empty_vect_desc;
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}
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ALCHLOG("Int %d reserved %d level %d %s hasIsr %d",
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x, interrupt_controller_hal_get_cpu_desc_flags(x,cpu)==INTDESC_RESVD, interrupt_controller_hal_get_level(x),
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interrupt_controller_hal_get_type(x)==INTTP_LEVEL?"LEVEL":"EDGE", interrupt_controller_hal_has_handler(x, cpu));
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if ( !is_vect_desc_usable(vd, flags, cpu, force) ) continue;
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if (flags&ESP_INTR_FLAG_SHARED) {
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//We're allocating a shared int.
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//See if int already is used as a shared interrupt.
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if (vd->flags&VECDESC_FL_SHARED) {
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//We can use this already-marked-as-shared interrupt. Count the already attached isrs in order to see
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//how useful it is.
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int no=0;
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shared_vector_desc_t *svdesc=vd->shared_vec_info;
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while (svdesc!=NULL) {
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no++;
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svdesc=svdesc->next;
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}
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if (no<bestSharedCt || bestLevel>interrupt_controller_hal_get_level(x)) {
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//Seems like this shared vector is both okay and has the least amount of ISRs already attached to it.
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best=x;
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bestSharedCt=no;
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bestLevel=interrupt_controller_hal_get_level(x);
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ALCHLOG("...int %d more usable as a shared int: has %d existing vectors", x, no);
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} else {
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ALCHLOG("...worse than int %d", best);
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}
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} else {
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if (best==-1) {
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//We haven't found a feasible shared interrupt yet. This one is still free and usable, even if
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//not marked as shared.
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//Remember it in case we don't find any other shared interrupt that qualifies.
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if (bestLevel>interrupt_controller_hal_get_level(x)) {
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best=x;
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bestLevel=interrupt_controller_hal_get_level(x);
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ALCHLOG("...int %d usable as a new shared int", x);
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}
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} else {
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ALCHLOG("...already have a shared int");
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}
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}
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} else {
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//Seems this interrupt is feasible. Select it and break out of the loop; no need to search further.
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if (bestLevel>interrupt_controller_hal_get_level(x)) {
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best=x;
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bestLevel=interrupt_controller_hal_get_level(x);
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} else {
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ALCHLOG("...worse than int %d", best);
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}
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}
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}
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ALCHLOG("get_available_int: using int %d", best);
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//Okay, by now we have looked at all potential interrupts and hopefully have selected the best one in best.
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return best;
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}
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//Common shared isr handler. Chain-call all ISRs.
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static void IRAM_ATTR shared_intr_isr(void *arg)
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{
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vector_desc_t *vd=(vector_desc_t*)arg;
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shared_vector_desc_t *sh_vec=vd->shared_vec_info;
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portENTER_CRITICAL_ISR(&spinlock);
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while(sh_vec) {
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if (!sh_vec->disabled) {
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if ((sh_vec->statusreg == NULL) || (*sh_vec->statusreg & sh_vec->statusmask)) {
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traceISR_ENTER(sh_vec->source+ETS_INTERNAL_INTR_SOURCE_OFF);
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sh_vec->isr(sh_vec->arg);
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// check if we will return to scheduler or to interrupted task after ISR
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if (!os_task_switch_is_pended(cpu_hal_get_core_id())) {
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traceISR_EXIT();
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}
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}
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}
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sh_vec=sh_vec->next;
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}
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portEXIT_CRITICAL_ISR(&spinlock);
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}
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#if CONFIG_APPTRACE_SV_ENABLE
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//Common non-shared isr handler wrapper.
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static void IRAM_ATTR non_shared_intr_isr(void *arg)
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{
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non_shared_isr_arg_t *ns_isr_arg=(non_shared_isr_arg_t*)arg;
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portENTER_CRITICAL_ISR(&spinlock);
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traceISR_ENTER(ns_isr_arg->source+ETS_INTERNAL_INTR_SOURCE_OFF);
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// FIXME: can we call ISR and check os_task_switch_is_pended() after releasing spinlock?
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// when CONFIG_APPTRACE_SV_ENABLE = 0 ISRs for non-shared IRQs are called without spinlock
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ns_isr_arg->isr(ns_isr_arg->isr_arg);
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// check if we will return to scheduler or to interrupted task after ISR
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if (!os_task_switch_is_pended(cpu_hal_get_core_id())) {
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traceISR_EXIT();
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}
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portEXIT_CRITICAL_ISR(&spinlock);
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}
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#endif
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//We use ESP_EARLY_LOG* here because this can be called before the scheduler is running.
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esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusreg, uint32_t intrstatusmask, intr_handler_t handler,
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void *arg, intr_handle_t *ret_handle)
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{
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intr_handle_data_t *ret=NULL;
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int force=-1;
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ESP_EARLY_LOGV(TAG, "esp_intr_alloc_intrstatus (cpu %u): checking args", cpu_hal_get_core_id());
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//Shared interrupts should be level-triggered.
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if ((flags&ESP_INTR_FLAG_SHARED) && (flags&ESP_INTR_FLAG_EDGE)) return ESP_ERR_INVALID_ARG;
|
|
//You can't set an handler / arg for a non-C-callable interrupt.
|
|
if ((flags&ESP_INTR_FLAG_HIGH) && (handler)) return ESP_ERR_INVALID_ARG;
|
|
//Shared ints should have handler and non-processor-local source
|
|
if ((flags&ESP_INTR_FLAG_SHARED) && (!handler || source<0)) return ESP_ERR_INVALID_ARG;
|
|
//Statusreg should have a mask
|
|
if (intrstatusreg && !intrstatusmask) return ESP_ERR_INVALID_ARG;
|
|
//If the ISR is marked to be IRAM-resident, the handler must not be in the cached region
|
|
//ToDo: if we are to allow placing interrupt handlers into the 0x400c0000—0x400c2000 region,
|
|
//we need to make sure the interrupt is connected to the CPU0.
|
|
//CPU1 does not have access to the RTC fast memory through this region.
|
|
if ((flags & ESP_INTR_FLAG_IRAM)
|
|
&& handler
|
|
&& !esp_ptr_in_iram(handler)
|
|
#if SOC_RTC_FAST_MEM_SUPPORTED
|
|
// IDF-3901.
|
|
&& !esp_ptr_in_rtc_iram_fast(handler)
|
|
#endif
|
|
) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
|
|
//Default to prio 1 for shared interrupts. Default to prio 1, 2 or 3 for non-shared interrupts.
|
|
if ((flags&ESP_INTR_FLAG_LEVELMASK)==0) {
|
|
if (flags&ESP_INTR_FLAG_SHARED) {
|
|
flags|=ESP_INTR_FLAG_LEVEL1;
|
|
} else {
|
|
flags|=ESP_INTR_FLAG_LOWMED;
|
|
}
|
|
}
|
|
ESP_EARLY_LOGV(TAG, "esp_intr_alloc_intrstatus (cpu %u): Args okay. Resulting flags 0x%X", cpu_hal_get_core_id(), flags);
|
|
|
|
//Check 'special' interrupt sources. These are tied to one specific interrupt, so we
|
|
//have to force get_free_int to only look at that.
|
|
if (source==ETS_INTERNAL_TIMER0_INTR_SOURCE) force=ETS_INTERNAL_TIMER0_INTR_NO;
|
|
if (source==ETS_INTERNAL_TIMER1_INTR_SOURCE) force=ETS_INTERNAL_TIMER1_INTR_NO;
|
|
if (source==ETS_INTERNAL_TIMER2_INTR_SOURCE) force=ETS_INTERNAL_TIMER2_INTR_NO;
|
|
if (source==ETS_INTERNAL_SW0_INTR_SOURCE) force=ETS_INTERNAL_SW0_INTR_NO;
|
|
if (source==ETS_INTERNAL_SW1_INTR_SOURCE) force=ETS_INTERNAL_SW1_INTR_NO;
|
|
if (source==ETS_INTERNAL_PROFILING_INTR_SOURCE) force=ETS_INTERNAL_PROFILING_INTR_NO;
|
|
|
|
//Allocate a return handle. If we end up not needing it, we'll free it later on.
|
|
ret=heap_caps_malloc(sizeof(intr_handle_data_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
|
|
if (ret==NULL) return ESP_ERR_NO_MEM;
|
|
|
|
portENTER_CRITICAL(&spinlock);
|
|
uint32_t cpu = cpu_hal_get_core_id();
|
|
//See if we can find an interrupt that matches the flags.
|
|
int intr=get_available_int(flags, cpu, force, source);
|
|
if (intr==-1) {
|
|
//None found. Bail out.
|
|
portEXIT_CRITICAL(&spinlock);
|
|
free(ret);
|
|
return ESP_ERR_NOT_FOUND;
|
|
}
|
|
//Get an int vector desc for int.
|
|
vector_desc_t *vd=get_desc_for_int(intr, cpu);
|
|
if (vd==NULL) {
|
|
portEXIT_CRITICAL(&spinlock);
|
|
free(ret);
|
|
return ESP_ERR_NO_MEM;
|
|
}
|
|
|
|
//Allocate that int!
|
|
if (flags&ESP_INTR_FLAG_SHARED) {
|
|
//Populate vector entry and add to linked list.
|
|
shared_vector_desc_t *sh_vec=malloc(sizeof(shared_vector_desc_t));
|
|
if (sh_vec==NULL) {
|
|
portEXIT_CRITICAL(&spinlock);
|
|
free(ret);
|
|
return ESP_ERR_NO_MEM;
|
|
}
|
|
memset(sh_vec, 0, sizeof(shared_vector_desc_t));
|
|
sh_vec->statusreg=(uint32_t*)intrstatusreg;
|
|
sh_vec->statusmask=intrstatusmask;
|
|
sh_vec->isr=handler;
|
|
sh_vec->arg=arg;
|
|
sh_vec->next=vd->shared_vec_info;
|
|
sh_vec->source=source;
|
|
sh_vec->disabled=0;
|
|
vd->shared_vec_info=sh_vec;
|
|
vd->flags|=VECDESC_FL_SHARED;
|
|
//(Re-)set shared isr handler to new value.
|
|
interrupt_controller_hal_set_int_handler(intr, shared_intr_isr, vd);
|
|
} else {
|
|
//Mark as unusable for other interrupt sources. This is ours now!
|
|
vd->flags=VECDESC_FL_NONSHARED;
|
|
if (handler) {
|
|
#if CONFIG_APPTRACE_SV_ENABLE
|
|
non_shared_isr_arg_t *ns_isr_arg=malloc(sizeof(non_shared_isr_arg_t));
|
|
if (!ns_isr_arg) {
|
|
portEXIT_CRITICAL(&spinlock);
|
|
free(ret);
|
|
return ESP_ERR_NO_MEM;
|
|
}
|
|
ns_isr_arg->isr=handler;
|
|
ns_isr_arg->isr_arg=arg;
|
|
ns_isr_arg->source=source;
|
|
interrupt_controller_hal_set_int_handler(intr, non_shared_intr_isr, ns_isr_arg);
|
|
#else
|
|
interrupt_controller_hal_set_int_handler(intr, handler, arg);
|
|
#endif
|
|
}
|
|
|
|
if (flags & ESP_INTR_FLAG_EDGE) {
|
|
interrupt_controller_hal_edge_int_acknowledge(intr);
|
|
}
|
|
|
|
vd->source=source;
|
|
}
|
|
if (flags&ESP_INTR_FLAG_IRAM) {
|
|
vd->flags|=VECDESC_FL_INIRAM;
|
|
non_iram_int_mask[cpu]&=~(1<<intr);
|
|
} else {
|
|
vd->flags&=~VECDESC_FL_INIRAM;
|
|
non_iram_int_mask[cpu]|=(1<<intr);
|
|
}
|
|
if (source>=0) {
|
|
esp_rom_route_intr_matrix(cpu, source, intr);
|
|
}
|
|
|
|
//Fill return handle data.
|
|
ret->vector_desc=vd;
|
|
ret->shared_vector_desc=vd->shared_vec_info;
|
|
|
|
//Enable int at CPU-level;
|
|
ESP_INTR_ENABLE(intr);
|
|
|
|
//If interrupt has to be started disabled, do that now; ints won't be enabled for real until the end
|
|
//of the critical section.
|
|
if (flags&ESP_INTR_FLAG_INTRDISABLED) {
|
|
esp_intr_disable(ret);
|
|
}
|
|
|
|
#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
|
|
//Extract the level from the interrupt passed flags
|
|
int level = esp_intr_flags_to_level(flags);
|
|
interrupt_controller_hal_set_int_level(intr, level);
|
|
|
|
if (flags & ESP_INTR_FLAG_EDGE) {
|
|
interrupt_controller_hal_set_int_type(intr, INTTP_EDGE);
|
|
} else {
|
|
interrupt_controller_hal_set_int_type(intr, INTTP_LEVEL);
|
|
}
|
|
#endif
|
|
|
|
portEXIT_CRITICAL(&spinlock);
|
|
|
|
//Fill return handle if needed, otherwise free handle.
|
|
if (ret_handle!=NULL) {
|
|
*ret_handle=ret;
|
|
} else {
|
|
free(ret);
|
|
}
|
|
|
|
ESP_EARLY_LOGD(TAG, "Connected src %d to int %d (cpu %d)", source, intr, cpu);
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler, void *arg, intr_handle_t *ret_handle)
|
|
{
|
|
/*
|
|
As an optimization, we can create a table with the possible interrupt status registers and masks for every single
|
|
source there is. We can then add code here to look up an applicable value and pass that to the
|
|
esp_intr_alloc_intrstatus function.
|
|
*/
|
|
return esp_intr_alloc_intrstatus(source, flags, 0, 0, handler, arg, ret_handle);
|
|
}
|
|
|
|
esp_err_t IRAM_ATTR esp_intr_set_in_iram(intr_handle_t handle, bool is_in_iram)
|
|
{
|
|
if (!handle) return ESP_ERR_INVALID_ARG;
|
|
vector_desc_t *vd = handle->vector_desc;
|
|
if (vd->flags & VECDESC_FL_SHARED) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
portENTER_CRITICAL(&spinlock);
|
|
uint32_t mask = (1 << vd->intno);
|
|
if (is_in_iram) {
|
|
vd->flags |= VECDESC_FL_INIRAM;
|
|
non_iram_int_mask[vd->cpu] &= ~mask;
|
|
} else {
|
|
vd->flags &= ~VECDESC_FL_INIRAM;
|
|
non_iram_int_mask[vd->cpu] |= mask;
|
|
}
|
|
portEXIT_CRITICAL(&spinlock);
|
|
return ESP_OK;
|
|
}
|
|
|
|
#if !CONFIG_FREERTOS_UNICORE
|
|
static void esp_intr_free_cb(void *arg)
|
|
{
|
|
(void)esp_intr_free((intr_handle_t)arg);
|
|
}
|
|
#endif /* !CONFIG_FREERTOS_UNICORE */
|
|
|
|
esp_err_t esp_intr_free(intr_handle_t handle)
|
|
{
|
|
bool free_shared_vector=false;
|
|
if (!handle) return ESP_ERR_INVALID_ARG;
|
|
|
|
#if !CONFIG_FREERTOS_UNICORE
|
|
//Assign this routine to the core where this interrupt is allocated on.
|
|
if (handle->vector_desc->cpu!=cpu_hal_get_core_id()) {
|
|
esp_err_t ret = esp_ipc_call_blocking(handle->vector_desc->cpu, &esp_intr_free_cb, (void *)handle);
|
|
return ret == ESP_OK ? ESP_OK : ESP_FAIL;
|
|
}
|
|
#endif /* !CONFIG_FREERTOS_UNICORE */
|
|
|
|
portENTER_CRITICAL(&spinlock);
|
|
esp_intr_disable(handle);
|
|
if (handle->vector_desc->flags&VECDESC_FL_SHARED) {
|
|
//Find and kill the shared int
|
|
shared_vector_desc_t *svd=handle->vector_desc->shared_vec_info;
|
|
shared_vector_desc_t *prevsvd=NULL;
|
|
assert(svd); //should be something in there for a shared int
|
|
while (svd!=NULL) {
|
|
if (svd==handle->shared_vector_desc) {
|
|
//Found it. Now kill it.
|
|
if (prevsvd) {
|
|
prevsvd->next=svd->next;
|
|
} else {
|
|
handle->vector_desc->shared_vec_info=svd->next;
|
|
}
|
|
free(svd);
|
|
break;
|
|
}
|
|
prevsvd=svd;
|
|
svd=svd->next;
|
|
}
|
|
//If nothing left, disable interrupt.
|
|
if (handle->vector_desc->shared_vec_info==NULL) free_shared_vector=true;
|
|
ESP_EARLY_LOGV(TAG, "esp_intr_free: Deleting shared int: %s. Shared int is %s", svd?"not found or last one":"deleted", free_shared_vector?"empty now.":"still in use");
|
|
}
|
|
|
|
if ((handle->vector_desc->flags&VECDESC_FL_NONSHARED) || free_shared_vector) {
|
|
ESP_EARLY_LOGV(TAG, "esp_intr_free: Disabling int, killing handler");
|
|
#if CONFIG_APPTRACE_SV_ENABLE
|
|
if (!free_shared_vector) {
|
|
void *isr_arg = interrupt_controller_hal_get_int_handler_arg(handle->vector_desc->intno);
|
|
if (isr_arg) {
|
|
free(isr_arg);
|
|
}
|
|
}
|
|
#endif
|
|
//Reset to normal handler:
|
|
interrupt_controller_hal_set_int_handler(handle->vector_desc->intno, NULL, (void*)((int)handle->vector_desc->intno));
|
|
//Theoretically, we could free the vector_desc... not sure if that's worth the few bytes of memory
|
|
//we save.(We can also not use the same exit path for empty shared ints anymore if we delete
|
|
//the desc.) For now, just mark it as free.
|
|
handle->vector_desc->flags&=~(VECDESC_FL_NONSHARED|VECDESC_FL_RESERVED|VECDESC_FL_SHARED);
|
|
//Also kill non_iram mask bit.
|
|
non_iram_int_mask[handle->vector_desc->cpu]&=~(1<<(handle->vector_desc->intno));
|
|
}
|
|
portEXIT_CRITICAL(&spinlock);
|
|
free(handle);
|
|
return ESP_OK;
|
|
}
|
|
|
|
int esp_intr_get_intno(intr_handle_t handle)
|
|
{
|
|
return handle->vector_desc->intno;
|
|
}
|
|
|
|
int esp_intr_get_cpu(intr_handle_t handle)
|
|
{
|
|
return handle->vector_desc->cpu;
|
|
}
|
|
|
|
/*
|
|
Interrupt disabling strategy:
|
|
If the source is >=0 (meaning a muxed interrupt), we disable it by muxing the interrupt to a non-connected
|
|
interrupt. If the source is <0 (meaning an internal, per-cpu interrupt), we disable it using ESP_INTR_DISABLE.
|
|
This allows us to, for the muxed CPUs, disable an int from the other core. It also allows disabling shared
|
|
interrupts.
|
|
*/
|
|
|
|
//Muxing an interrupt source to interrupt 6, 7, 11, 15, 16 or 29 cause the interrupt to effectively be disabled.
|
|
#define INT_MUX_DISABLED_INTNO 6
|
|
|
|
esp_err_t IRAM_ATTR esp_intr_enable(intr_handle_t handle)
|
|
{
|
|
if (!handle) return ESP_ERR_INVALID_ARG;
|
|
portENTER_CRITICAL_SAFE(&spinlock);
|
|
int source;
|
|
if (handle->shared_vector_desc) {
|
|
handle->shared_vector_desc->disabled=0;
|
|
source=handle->shared_vector_desc->source;
|
|
} else {
|
|
source=handle->vector_desc->source;
|
|
}
|
|
if (source >= 0) {
|
|
//Disabled using int matrix; re-connect to enable
|
|
esp_rom_route_intr_matrix(handle->vector_desc->cpu, source, handle->vector_desc->intno);
|
|
} else {
|
|
//Re-enable using cpu int ena reg
|
|
if (handle->vector_desc->cpu!=cpu_hal_get_core_id()) return ESP_ERR_INVALID_ARG; //Can only enable these ints on this cpu
|
|
ESP_INTR_ENABLE(handle->vector_desc->intno);
|
|
}
|
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t IRAM_ATTR esp_intr_disable(intr_handle_t handle)
|
|
{
|
|
if (!handle) return ESP_ERR_INVALID_ARG;
|
|
portENTER_CRITICAL_SAFE(&spinlock);
|
|
int source;
|
|
bool disabled = 1;
|
|
if (handle->shared_vector_desc) {
|
|
handle->shared_vector_desc->disabled=1;
|
|
source=handle->shared_vector_desc->source;
|
|
|
|
shared_vector_desc_t *svd=handle->vector_desc->shared_vec_info;
|
|
assert( svd != NULL );
|
|
while( svd ) {
|
|
if ( svd->source == source && svd->disabled == 0 ) {
|
|
disabled = 0;
|
|
break;
|
|
}
|
|
svd = svd->next;
|
|
}
|
|
} else {
|
|
source=handle->vector_desc->source;
|
|
}
|
|
|
|
if (source >= 0) {
|
|
if ( disabled ) {
|
|
//Disable using int matrix
|
|
esp_rom_route_intr_matrix(handle->vector_desc->cpu, source, INT_MUX_DISABLED_INTNO);
|
|
}
|
|
} else {
|
|
//Disable using per-cpu regs
|
|
if (handle->vector_desc->cpu!=cpu_hal_get_core_id()) {
|
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
|
return ESP_ERR_INVALID_ARG; //Can only enable these ints on this cpu
|
|
}
|
|
ESP_INTR_DISABLE(handle->vector_desc->intno);
|
|
}
|
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
|
return ESP_OK;
|
|
}
|
|
|
|
void IRAM_ATTR esp_intr_noniram_disable(void)
|
|
{
|
|
portENTER_CRITICAL_SAFE(&spinlock);
|
|
uint32_t oldint;
|
|
uint32_t cpu = cpu_hal_get_core_id();
|
|
uint32_t non_iram_ints = non_iram_int_mask[cpu];
|
|
if (non_iram_int_disabled_flag[cpu]) {
|
|
abort();
|
|
}
|
|
non_iram_int_disabled_flag[cpu] = true;
|
|
oldint = interrupt_controller_hal_read_interrupt_mask();
|
|
interrupt_controller_hal_disable_interrupts(non_iram_ints);
|
|
// Disable the RTC bit which don't want to be put in IRAM.
|
|
rtc_isr_noniram_disable(cpu);
|
|
// Save disabled ints
|
|
non_iram_int_disabled[cpu] = oldint & non_iram_ints;
|
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
|
}
|
|
|
|
void IRAM_ATTR esp_intr_noniram_enable(void)
|
|
{
|
|
portENTER_CRITICAL_SAFE(&spinlock);
|
|
uint32_t cpu = cpu_hal_get_core_id();
|
|
int non_iram_ints = non_iram_int_disabled[cpu];
|
|
if (!non_iram_int_disabled_flag[cpu]) {
|
|
abort();
|
|
}
|
|
non_iram_int_disabled_flag[cpu] = false;
|
|
interrupt_controller_hal_enable_interrupts(non_iram_ints);
|
|
rtc_isr_noniram_enable(cpu);
|
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
|
}
|
|
|
|
//These functions are provided in ROM, but the ROM-based functions use non-multicore-capable
|
|
//virtualized interrupt levels. Thus, we disable them in the ld file and provide working
|
|
//equivalents here.
|
|
|
|
|
|
void IRAM_ATTR ets_isr_unmask(uint32_t mask) {
|
|
interrupt_controller_hal_enable_interrupts(mask);
|
|
}
|
|
|
|
void IRAM_ATTR ets_isr_mask(uint32_t mask) {
|
|
interrupt_controller_hal_disable_interrupts(mask);
|
|
}
|
|
|
|
void esp_intr_enable_source(int inum)
|
|
{
|
|
interrupt_controller_hal_enable_interrupts(1 << inum);
|
|
}
|
|
|
|
void esp_intr_disable_source(int inum)
|
|
{
|
|
interrupt_controller_hal_disable_interrupts(1 << inum);
|
|
}
|