kopia lustrzana https://github.com/espressif/esp-idf
68 wiersze
3.4 KiB
C
68 wiersze
3.4 KiB
C
#include "hal/spi_slave_hal.h"
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#include "hal/spi_ll.h"
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#include "soc/soc_caps.h"
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#if SOC_GDMA_SUPPORTED
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#include "soc/gdma_struct.h"
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#include "hal/gdma_ll.h"
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#define spi_dma_ll_rx_reset(dev) gdma_ll_rx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL)
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#define spi_dma_ll_tx_reset(dev) gdma_ll_tx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);
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#define spi_dma_ll_rx_enable_burst_data(dev, enable) gdma_ll_rx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_ll_tx_enable_burst_data(dev, enable) gdma_ll_tx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_ll_rx_enable_burst_desc(dev, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_ll_tx_enable_burst_desc(dev, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_set_rx_channel_priority(dev, priority) gdma_ll_rx_set_priority(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, priority);
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#define spi_dma_set_tx_channel_priority(dev, priority) gdma_ll_tx_set_priority(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, priority);
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#define spi_dma_enable_out_auto_wrback(dev, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_set_out_eof_generation(dev, enable) gdma_ll_tx_set_eof_mode(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_connect_rx_channel_to_periph(dev, periph_id) gdma_ll_rx_connect_to_periph(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, periph_id);
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#define spi_dma_connect_tx_channel_to_periph(dev, periph_id) gdma_ll_tx_connect_to_periph(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, periph_id);
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#define spi_dma_ll_rx_start(dev, addr) do {\
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gdma_ll_rx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\
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gdma_ll_rx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\
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} while (0)
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#define spi_dma_ll_tx_start(dev, addr) do {\
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gdma_ll_tx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\
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gdma_ll_tx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\
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} while (0)
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#endif
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static void s_spi_slave_hal_dma_init_config(const spi_slave_hal_context_t *hal)
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{
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spi_dma_ll_rx_enable_burst_data(hal->dma_in, 1);
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spi_dma_ll_tx_enable_burst_data(hal->dma_out, 1);
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spi_dma_ll_rx_enable_burst_desc(hal->dma_in, 1);
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spi_dma_ll_tx_enable_burst_desc(hal->dma_out, 1);
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}
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void spi_slave_hal_init(spi_slave_hal_context_t *hal, const spi_slave_hal_config_t *hal_config)
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{
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memset(hal, 0, sizeof(spi_slave_hal_context_t));
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spi_dev_t *hw = SPI_LL_GET_HW(hal_config->host_id);
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hal->hw = hw;
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hal->dma_in = hal_config->dma_in;
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hal->dma_out = hal_config->dma_out;
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s_spi_slave_hal_dma_init_config(hal);
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spi_ll_slave_init(hal->hw);
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//Force a transaction done interrupt. This interrupt won't fire yet because we initialized the SPI interrupt as
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//disabled. This way, we can just enable the SPI interrupt and the interrupt handler will kick in, handling
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//any transactions that are queued.
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spi_ll_set_int_stat(hal->hw);
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spi_ll_enable_int(hal->hw);
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}
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void spi_slave_hal_setup_device(const spi_slave_hal_context_t *hal)
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{
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spi_ll_set_rx_lsbfirst(hal->hw, hal->rx_lsbfirst);
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spi_ll_set_tx_lsbfirst(hal->hw, hal->tx_lsbfirst);
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spi_ll_slave_set_mode(hal->hw, hal->mode, hal->use_dma);
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}
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void spi_slave_hal_deinit(spi_slave_hal_context_t *hal)
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{
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} |